E6G 6 PIN IC
Abstract: No abstract text available
Text: RGB528A 1.0 Microprocessor Access A s seen on the m icroprocessor b u s there are eight I/O addresses, selected by RS[2:0]. T w o indirect schem es are used to access all of the internal registers and a rra ys th ro u g h these eight p rim a ry I/O addresses.
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RGB528A
E6G 6 PIN IC
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B60V
Abstract: No abstract text available
Text: RGB526/RGB526DB 5.0 5.1 VRAM Pixel Formats 5.3 Bit Ordering With 4 BPP format 8 pixels 32 bit VRAM width or 16 pixels (64 bit VRAM width) are obtained for each pixel port data access. As noted above the default access of the two pixels within each byte are high-to-low:
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RGB526/RGB526DB
M526DB,
B60V
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Untitled
Abstract: No abstract text available
Text: RGB526/RGB526DB 13.0 Pin Descriptions Table 11. Pin Descriptions Signal ¡1 1 1 1 Description xxiÊxxx REFCLK I 80 FS[1:0] I 96,83 DDOTCLK o 116 SCLK 113 LCLK I 109 SYSCLK o 75 PIX[63:0] I 10 «1ft *7 66,65,64, ÎP3 1.22 121320.119,118, 117 140.139,138,137,136,
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RGB526/RGB526DB
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RGB525
Abstract: E4RE
Text: RGB525 3.0 M o d e s o f O pe ratio n Pixel da ta can come from the VGA port or the VRAM pixel port, as selected by the P O R T SEL bit of the M is cellaneous Contr ol 2 register. If the VRAM pixel p ort is selected, the pixel f o r m a t can be 4 B P P bits p e r pixel , 8 BPP, 15/16 BPP, 24 B P P
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RGB525
RGB525
E4RE
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RGB525
Abstract: No abstract text available
Text: RGB525 16.0 C h a n g e S u m m a r y Table 19. Sum m ary o f C hanges D a te C hanges 9/9 3 1. 3/9 4 1. F i r s t p u b l i c a t i o n , P R E L I M I N A R Y i n f o r m a t i o n p r i o r to p r o d u c t b u i l d . M o v e d / C h a n g e d s o m e p i n a s s i g n m e n t s to m i n i m i z e c h a n c e o f c o u p l i n g fr o m c a r d w i r i n g to P L L s u p p o r t
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RGB525
RGB525
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0X0009
Abstract: 0x0070
Text: RGB526/RGB526DB Table 10. Internal Register Sum m ary Continued 11.0 Internal Register - Summary R S[2:0] Index R/W R eset V alue 110 0x0015 y 0x08 SY SCLK N (Sy stem P L L Reference D ivider) 110 0x0016 y 0x41 SY SCLKM (Sy stem P L L VCO D ivider) 110 0x0017
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RGB526/RGB526DB
0x0015
0x0092
0x0100
0x04ff
0x0500
0x07fT
0x0071
0x0072
0x0073
0X0009
0x0070
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rgb525
Abstract: No abstract text available
Text: RGB525 14.0 P a c k a g e I n f o r m ation 1-2 1 3 3 0.0 0 1. 197 (30 .4 0 ' 15.0 O r d e r i n g In f o r m a t i o n Table 18. Part N um bers Part N um ber Speed I BM 3 7 - RGB5 2 5 L - 1 7 C C 170 MH z IB M3 7- RGB5 25L-22CC 220 MH z I B M 3 7 - R G B 5 2 5 L - 2 5 C C (*
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RGB525
25L-22CC
rgb525
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Untitled
Abstract: No abstract text available
Text: RGB528A 1.0 Microprocessor Access As seen on the microprocessor bus there are eight I/O addresses, selected by RS[2:0], Two indirect schemes are used to access all of the internal registers and arrays through these eight primary I/O addresses. The first scheme is standard VGA, and operates when
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RGB528A
256x8
RGB528,
RGB528A
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RGB524
Abstract: RGB526/RGB526DB
Text: RGB526/RGB526DB 1.0 Microprocessor Access As seen on th e m icroprocessor bus th e re are eight I/O addresses, selected by RS[2:0]. Two indirect schemes are used to access all of th e in te rn a l registers and arrays through th ese eight prim ary I/O addresses.
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RGB526/RGB526DB
256x8
RGB524
RGB526/RGB526DB
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RS-343-A
Abstract: RS-343A
Text: RGB526/RGB526DB 15.0 Video Waveforms WHITE BLACK BLANK SYNC Table 17. Composite Video Output Waveform D o u b ly te r m in a t e d 75 o h m s, R R E F = 698 o h m s Sync No No Y es P ed esta l No Y es No V a lu e IR E WHITE mA V 18.65 0.70 100 mA V 19.05 0.714
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RGB526/RGB526DB
RS-343A
RS-343-A
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RGB525
Abstract: No abstract text available
Text: RGB525 4.0 Controls 4.1 B l a n k a nd B o r d e r C on t r o l T h e B L A N K a n d B O R D E R s i g n a l s c o n t r o l the w a y in whi c h d a t a is p r e s e n t e d to t he D A C s . T h e s e cont r ol s i g n a l s a r e u s e d to d e t e r m i n e w h e n p i x e l d a t a is v a l i d ,
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RGB525
RGB525
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0x008F
Abstract: 0x0070 0x0091 0X0044 0X00
Text: RGB525 9.0 I nt er nal R e g i s t e r - S u m m a r y Ta bk', ÿ is a s u m m a r y of the in t e r n a l registers, with more detailed descriptions for the D irect Access Re g is ters, Ind ex ed Registers, Pixel R e p re s e n ta t io n , F r e quen cy Selection, Cursor, B o rder Color a nd Diagnostic
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RGB525
0x0014
0x0015
0x001f
0x0020
0x0021
0x0022
0x0023
0x0024
0x0025
0x008F
0x0070
0x0091
0X0044
0X00
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Untitled
Abstract: No abstract text available
Text: RGB528A 8.0 Power Management The following registers are used to control power dissipation: □ Power Managem ent index 0x0005 □ Miscellaneous Clock Control (index 0x0002) □ Sync Control (index 0x0003) □ Miscellaneous Control 1 (index 0x0070) 8.3 Clocking Power
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RGB528A
0x0005)
0x0002)
0x0003)
0x0070)
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Untitled
Abstract: No abstract text available
Text: RGB528A 4.0 Controls 4.1 Blank and Border Control T h e B L A N K and B O R D E R / O E sig n a ls control the w ay in w hich data is presented to the D A C s. T h e se control sig n a ls are used to determ ine w he n pixel data is valid, w he n the border color is to be displayed, w here the cu r
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RGB528A
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Untitled
Abstract: No abstract text available
Text: RGB528A 12.0 Pin Descriptions Table 11. Pin Descriptions Signal Typ e Pin s Description Clocks and Clock Controls R EFCLK I 117 Reference Clock. A fixe d fre q u e n cy o f 2 M H z to 100 M H z a pplied to th is p in provides th e reference clock fo r th e p ro g ra m m a b le pixel and system clock
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RGB528A
PIX156)
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RGB514
Abstract: RGB528A
Text: RGB528A B.O Switching Into VGA Mode The RGB528A has two fundam ental modes of operation which depend on the input pixel port selected, VGA or V R A M . The port is selected w ith the "PORT SEL" bit bit 0 of Miscellaneous Control 2 register. But now set bits 7 and 6 to ’00' (PC LK SEL =
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RGB528A
RGB528A
RGB513,
RGB514,
RGB525
RGB514
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Untitled
Abstract: No abstract text available
Text: RGB526/RGB526DB 1.0 Microprocessor Access As seen on the m icroprocessor bus there are eight I/O addresses, selected by RS[2:0]. Two indirect schem es are used to access all of the internal registers and arrays through th ese eight prim ary I/O addresses.
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RGB526/RGB526DB
0x0100.
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Untitled
Abstract: No abstract text available
Text: RGB525 12.0 E lectrical and T im in g S p e c i f i c a t i o n s Table 12. R ecom m ended Operating C o n d itio n s 170 M H z Param eter 220 M H z 250 M H z 250 M H z S ym bol Units Min. Power S upply Max. M i n. Max. M i n. Max. Min. Max. V DD , D A C V D D , P L L V D D
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RGB525
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Untitled
Abstract: No abstract text available
Text: RGB526/RGB526DB 18.0 Change Summary Table 20. Summary of Changes Date Changes 04/17/95 1. 09/25/95 This revision adds the RGB526DB product; the document becomes a combined RGB526/RGB526DB data sheet. All of the changes are related to adding the RGB526DB product information:
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RGB526/RGB526DB
RGB526DB
RGB526/RGB526DB
RGB526
RGB526DBj:
RGB526DB.
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RGB525
Abstract: No abstract text available
Text: RGB525 1.0 M icroprocessor Access As s e e n o n t h e m i c r o p r o c e s s o r b u s t h e r e a r e e i g h t I/O a d d r e s s e s , s e l e c t e d b y RS[ 2: 0] . T w o i n d i r e c t s c h e m e s a r e u s e d to a c c e s s a l l o f t h e i n t e r n a l r e g i s t e r s a n d a r r a y s
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RGB525
RGB525
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Untitled
Abstract: No abstract text available
Text: RGB526/RGB526DB N gives finer control in program m ing for the desired output frequencies, and allows the in ternal operat ing points of the P L L s to be fine tuned. Appendix A.O RGB526, RGB526DB Comparison The R G B 526D B is a su perset of th e R G B 526 th a t adds
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RGB526/RGB526DB
RGB526,
RGB526DB
0x000d
B526D
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RGB525
Abstract: No abstract text available
Text: RGB528A Appendix O n th e RGB525 b it 4 o f th e P L L C o n tro l 1 re g iste r selects th e reference source o f th e P L L , R E F C L K or E X T C L K . On th e R G B 528A th is b it is reserved. A.0 Relationship to RGB525 B its 7 - 6 of th e M iscellaneous C o n tro l 2 register
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RGB528A
RGB525
RGB528A
RGB525
RGB525.
B528A
0x0090,
0x0091,
0x0092,
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37RGB526
Abstract: No abstract text available
Text: RGB526/RGB526DB 12.0 Register Descriptions 12.1 Pixel Mask Direct Access Registers T h e d irec t access re g iste rs a re a d d re ssed u sin g RS[2:0] in p u ts. RS[2:0]: 010 Access: R ead /W rite Power on Value: U n d efin ed Palette Address Write Mode
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RGB526/RGB526DB
37RGB526
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rgb52
Abstract: No abstract text available
Text: RGB528A 11.0 Register Descriptions pixel Mask / 11.1 7 6 The direct access registers are addressed using RS[2:0] inputs. RS[2:0]: 010 Access: Read/Write Bits 7 - 0 6 5 4 3 2 1 / W RITE Address RS[2:0]: 000 Access: Read/Write Pow er on Value: Undefined Bits 7 - 0
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RGB528A
rgb52
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