NM95MS18

Contextual Info: NM95MS18 User’s Guide Register Summary Following is a list of registers implemented on NM95MS18 Plugn-Play controller. Registers located from 0x00 to 0x0F Word address are specific to NM95MS18 and are not part of registers defined by Plug-n-Play specification. NM95MS18 initializes itself

MSL260G

Abstract: MSL-260-G D0806 R0807 T0803 D0802 D0807 RDD0804 D0808 5 pin reset ic ARB
Contextual Info: Using the Intel 80960 CA with the PCI 9060 PCI evaluation board, Schematics PLX TECHNOLOGY PCI9060 Demo Board I/O MAP 06/16/96 PCI Configuration Registers Address BIT Function 0x00000000 0-15 Vendor ID, Allocated to PLX by PCI SIG (Read-only) (Default = 10B5)

NM95MS18

Abstract: ISA BUS structure
Contextual Info: Mohan Prasad • June ‘97 NM95MS18 USER'S GUIDE Register Summary Following is a list of registers implemented on NM95MS18 Plug-n-Play controller. Registers located from 0x00 to 0x0F Word address are specific to NM95MS18 and are not part of registers defined

564-0700-444

Contextual Info: 3mm LED CBI Circuit Board Indicator Tri-Level Dialight 564-0x00-xxx PART NO. 4.32 [.170] MAX HIGH EFFICIENCY - LED TYPE 01 11.56 [.455] 2.62 [.103 ±.015] COLOR* 564-0100-111 564-0100-132 564-0100-222 564-0100-777 3.05 [.120] 5.08 [.200] Red-Red-Red Red-Yellow-Green

MC68HC05

Abstract: MC68HC11 MPC823 MC68302 MC68328 MC68360
Contextual Info: Communication Processor Module The expected results are as follows: SMC • The TX buffer descriptor Ep0 CONTROL/STATUS field must contain 0x3800. • The TX buffer descriptor (Ep0) DATA LENGTH field must contain 0x0003. • The TX buffer descriptor (Ep1) CONTROL/STATUS field must contain 0x3c80.

25e5

Abstract: GR253-CORE GR-253 TMPR28051 VT13 GR-253 J0 byte length 14
Contextual Info: Advisory August 5, 1999 TMPR28051 STS-1/AU-3 STM-0 Mapper Device Advisory for Version 5 of the Device Register Architecture (RA) Map RA-1. Reset Bit The software reset bit (bit 0) of register 0x00 is not functional. RA-2. Transmit Path AIS Insert Bit The TXPAISINS bit (bit 5) of register 0x01 produces both AIS-P and AIS-L.

0x00000010

Abstract: 0x300000C0 0x0000000b E 32.0000 C 000D 10B5 0x300000C4 0x10000000-0x2FFFFFFF
Contextual Info: PLX Technology PCI9060/68040 DEMO Memory Map 06/24/96 PCI Configuration Registers PCI CFG Offset BIT 0x00000000 0-15 0x00000002 0-15 Function Vendor ID, Allocated to PLX by PCI SIG Read-only (Default = 10B5) Device ID, Allocated by PLX (Read-only) (Default = 9060)

0x00000564

Abstract: 0x00000404 0x00000532 0x0000047C 0x000005BE STI3400 0x0000040A sgs 8 r 15 93CS46 0x0000045C
Contextual Info: PLX Technology SGS PCI MPEG Board I/O MAP 07/15/96 PCI Configuration Registers PCI CFG Offset 0x00000000 0x00000002 BIT 0-15 0-15 Function Vendor ID, Allocated to PLX by PCI SIG Read-only (Default = 10B5) Device ID, Allocated by PLX (Read-only) (Default = 9060)

80C517

Abstract: DS80C320 EMUL51-PC OMF51
Contextual Info: CHIPTOOLS, INC. ChipView -51 Chip Vie w®-51 High-Level/Low-level Debugger *»• MlUIO •ifhhta ,’l t i t r«4 <0x«K0«m ,7 f IM S 'ièxw m yi 0X0006u (0 x0 00 0 >> J i t hi® CftM tNM tem ,’l t i b i U »ML. ▲ No learning curve— ChipView-51 is keycom patible with B orlands’s popular turbo

Contextual Info: CY7C63411/12/13 TfffFnnmrm.v CY7C63511/12/13 ,/C IP R E S S 6.0 Memory Organization 6.1 Program Memory Organization after reset 14-bit PC Address -^ 0x0000 Program execution begins here after a reset. 0x0002 USB Bus Reset interrupt vector 0x0004 128 is timer interrupt vector

0X0009

Abstract: 0x0070
Contextual Info: RGB526/RGB526DB Table 10. Internal Register Sum m ary Continued 11.0 Internal Register - Summary R S[2:0] Index R/W R eset V alue 110 0x0015 y 0x08 SY SCLK N (Sy stem P L L Reference D ivider) 110 0x0016 y 0x41 SY SCLKM (Sy stem P L L VCO D ivider) 110 0x0017

Contextual Info: Card-Edge Connectors Accessories and Mating Cable Accessories Contact Quantity 10 16 20 26 34 40 50 60 64 *For drawing see page 92. Mating Cable Part Number 3358-0X00 3358-0X01 3358-0X02 3308-0X00 3368-0X01 3368-0X02 3461-0X00 3461-0X01 3461-0X02 3461-0X41

Contextual Info: 2mm FB Amphenol Part Number: 2021-AP6P-502-0X00 5 row Power Female Right-Angle Press- fit - In accordance to IEC 1076-4-104 - Modular design guarantees flexibility - Press block ensures accurate position of press fit tails for easy mounting - 12mm power modules are form-and

0x0002

Abstract: ADSP-21000 0X0040
Contextual Info: Interrupt Vector Addresses IRPTL/ IMASK Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Vector Address* 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x50 0x54

Contextual Info: PSoC Creator Component Datasheet Die Temperature DieTemp 1.70 Features • Accuracy of ±5 °C • Range –40 °C to +140 °C (0xFFD8 to 0x008C)  Blocking and nonblocking API  Supports only PSoC 3 ES2 silicon with date code 1005 or later and Production PSoC 3

0x8b00

Abstract: 0x010A 0X13 Y000 0x051B B5M2R 0x018E 0X23 0X34C 0x390
Contextual Info: RABBIT 4000 MICROPROCESSOR Memory Management Unit Processor Control MUST = 0 RESERVED GCSR 0x00 MUST = 0 RD ONLY GPSCR (0x0D) 000 = SELF-TIMED CS DISABLE 7 001 = 230 ns 010 = 170 ns SELF-TIMED CS 011 = 110 ns READ ONLY 100 = 290 ns 101 = 230 ns SELF-TIMED CS

Contextual Info: RGB640 10.0 Register Descriptions 10.1 0x0000 Identification 7 6 5 4 3 2 1 IDLO POR: 0x1 C Bits 7 0: ID LO - The low byte of the product identification code. 0x1 C 10.2 0x0001 Identification / Revision Level 7 6 5 4 3 REV 4: Bits 3 0: 48 1 IDHI 0x12 POR:

Contextual Info: RGB528A 8.0 Power Management The following registers are used to control power dissipation: □ Power Managem ent index 0x0005 □ Miscellaneous Clock Control (index 0x0002) □ Sync Control (index 0x0003) □ Miscellaneous Control 1 (index 0x0070) 8.3 Clocking Power

PSOC3

Contextual Info: PSoC Creator Component Datasheet Die Temperature DieTemp 2.0 Features • Accuracy of ±5 °C • Range –40 °C to +140 °C (0xFFD8 to 0x008C)  Blocking and non-blocking API  Does not support PSoC 5 silicon General Description The Die Temperature (DieTemp) component provides an API to acquire the temperature of the

Contextual Info: PSoC Creator Component Data Sheet Die Temperature DieTemp 1.50 Features • Accuracy of +/-5° C • Range -40° C to +140° C (0xffd8 to 0x008c) • Blocking and non blocking API General Description The Die Temperature (DieTemp) component provides an API to acquire the temperature of the

Contextual Info: ¿¿PD30111 NEC 6. DMAAU DMA ADDRESS UNIT DMAAU controls the addresses for the DMA operations between A lU /lrD A 4-M bps communication module (FIR) and memory. The DMA start address of each DMA channel can be specified in a range of 0x0000 0000 through 0x01 FF FFFE

0X000F

Abstract: C800 MPC555 c880 0000FFFF MPC566
Contextual Info: Motorola MPC5xx Memory Maps Address* 0x0000 0x0003 0x0004 0x0006 0x0007 0x0007 0x0008 0x000F 0x0010 0x002F 0x002F 0x002F 0x002F 0x002F 0x002F 0x002F 0x002F 0x002F 0x002F 0x002F 0x002F 0x002F 0x002F 0x002F 0x002F 0x002F 0x0030 0x0030 0x0030 0x0030 0x0030 0x0030

Contextual Info: Registers NOTE: For a sum m ary o f all registers, refer to the R egister Sum m ary section at the end o f this chapter. Control Registers 0x00— Mode Control Register CROO 7 6 5 4 3 2 1 LineLp SourceLp TxA lm l TxAlmO ExtOvh ExtCBit E3Frm CBItP/DL LineLp

Contextual Info: MM Registers - For a summary of all registers refer to the Register Summary section at the end of this chapter. All reserved bits must be written to a zero. NOTE: Control Registers 0x00— DS1/DS2 Output Control Register CR00