PO44V5 Search Results

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Catalog Datasheet	MFG & Type	PDF	Document Tags
circuit diagram of Tri-State Buffer using CMOS Abstract: verilog code for UART with BIST capability block diagram for UART with BIST capability tri state AT28 vhdl code for flip-flop vhdl pid verilog code pid controller free vhdl code for usart Text: Features • 0.5 µm Drawn Gate Length 0.45 µm Leff Sea-of-Gates Architecture with • • • • • Triple-level Metal Embedded E2 Memory up to 256 Kb 3.3V Operation with 5.0V Tolerant Input and Output Buffers High-speed, 200 ps Gate Delay, 2-input NAND, FO = 2 Nominal	Original	PDF	10T/100 ATL50/E2 1173D 11/99/1M circuit diagram of Tri-State Buffer using CMOS verilog code for UART with BIST capability block diagram for UART with BIST capability tri state AT28 vhdl code for flip-flop vhdl pid verilog code pid controller free vhdl code for usart
AOI222 Abstract: AOI2223 AOI222H MH1099 MH1242 0.35-um CMOS standard cell library inverter Text: Features • High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 Nominal • Up to 1.6 Million Used Gates and 596 Pads, with 3.3V, 3V, and 2.5V Libraries • System Level Integration Technology Cores on Request: SRAM and TRAM (Gate Level or Embedded) • I/O Interfaces:	Original	PDF	5962-01B01 4138E AOI222 AOI2223 AOI222H MH1099 MH1242 0.35-um CMOS standard cell library inverter
AVR 8515 microcontroller Abstract: FPGA AMI coding decoding tri state AOI222 AOI2223 AOI2223H AOI222H ATL35 0.35-um CMOS standard cell library inverter Text: Features • System Level Integration Technology • 0.35 µm Geometry in Triple-level Metal • I/O Interfaces; CMOS, LVTTL, LVDS, PCI, USB – Output Currents up to 20 mA, 5V Tolerant I/O • Embedded Flash Memory with Capacities of 1Mbit, 2Mbit or 4Mbit	Original	PDF	22-bit 16-bit 1184B 03/00/xM AVR 8515 microcontroller FPGA AMI coding decoding tri state AOI222 AOI2223 AOI2223H AOI222H ATL35 0.35-um CMOS standard cell library inverter
tristate buffer Abstract: smd transistor AO HEX TO DECIMAL tristate buffer cmos A101 A201 MH1099E MH1156E PO11F MH1332E Text: Features • High Speed - 180 ps Gate Delay - 2 Input NAND, FO = 2 nominal • Up to 1.198M Used Gates and 512 Pads with 3.3V, 3V and 2.5V Libraries when Tested to Space Quality Grades • Up to 1.6M Used Gates and 596 Pads with 3.3V, 3V and 2.5V Libraries when Tested to	Original	PDF	4110F tristate buffer smd transistor AO HEX TO DECIMAL tristate buffer cmos A101 A201 MH1099E MH1156E PO11F MH1332E
54175 Abstract: PO11V5 16889 49035 56374 28548 58128 13.562 93408 atmel 246 Text: ERRATA SHEET DATE: April 2009 TO: Aerospace customers SUBJECT: 5V COMPLIANT BUFFERS WITH CORE POWERED AT 2.5V A 5V compliant buffer is a buffer powered by a 5V supply which is able to tolerate with negligible leakage current and without any reliability problems 5V signals (input buffer and pullup/pull-down) or drive 5V signals on its output (output buffer).	Original	PDF	125pf 130pf 135pf 140pf 145pf 150pf 155pf 160pf 165pf 170pf 54175 PO11V5 16889 49035 56374 28548 58128 13.562 93408 atmel 246
atmel 216 Abstract: ECL IC NAND CQFP 256 PIN actel Atmel 642 PO22 tri state ATL35 atmel 334 20PCI atmel h 952 Text: Features • High-speed - 150 ps Gate Delay - 2-input NAND, FO = 2 nominal • Up to 2.7 Million Used Gates and 976 Pins • System Level Integration Technology – Cores: ARM7TDMI and AVR RISC Microcontrollers, OakDSP™ and LodeDSPCores™, 10T/100 Ethernet MAC, USB and PCI Cores	Original	PDF	10T/100 ATL35 0802E 10/99/0M atmel 216 ECL IC NAND CQFP 256 PIN actel Atmel 642 PO22 tri state atmel 334 20PCI atmel h 952
PO77F Abstract: PO55F 090569 PO55V 24236 PO11F 328-529 po11s PX2L PO22 Text: ATL35 I/O Buffer Cell Library-1.4-09/99 ATL35 0.35µ I/O Buffer Cell Library I/O Buffer Naming Convention . 8-2 I/O Site: Pad and Sub-Sections . 8-2	Original	PDF	ATL35 PO22V5 PO44V5 PO77F PO55F 090569 PO55V 24236 PO11F 328-529 po11s PX2L PO22
PO88 Abstract: ttl buffer AOI222 AOI2223 AOI2223H AOI222H MH1099 MH1242 PRD21 PRD29V5 Text: Features • High Speed - 170 ps Gate Delay - 2 input NAND, FO=2 nominal • Up to 1.6 Million Used Gates and 596 pads, with 3.3V, 3V, and 2.5V libraries • System Level Integration Technology Cores on request: SRAM and TRAM (Gate Level or Embedded) • I/O Interfaces:	Original	PDF	250MHz 220MHz 800MHz 5962-01B01 PO88 ttl buffer AOI222 AOI2223 AOI2223H AOI222H MH1099 MH1242 PRD21 PRD29V5
TEMIC PLD Abstract: PRU10 PRD8 buffer 8x Structure of D flip-flop DFFSR AOI222 AOI2223 AOI2223H AOI222H MH1099 Text: MH1 1.6 Million gates Sea of Gates / Embedded Arrays 1. Description The MH1 Series Gate Array and Embedded Array families from TEMIC are fabricated in a 0.35µ CMOS process, with up to 3 levels of metal. This family features arrays with up to 1.6 million routable gates and 600 pins. The	Original	PDF
Transistor Equivalent list po55 Abstract: Structure of D flip-flop DFFSR tristate buffer sis 968 PO-44Z PRU11 AC/DC drive nec 78054 PO22 tristate buffer cmos Text: Features • High Speed - 180 ps Gate Delay - 2 input NAND, FO=2 nominal • Up to 1.198 M Used Gates and 512 Pads with 3.3 V, 3V and 2.5V libraries when tested to space quality grades • Up to 1.6M Used Gates and 596 Pads with 3.3 V, 3V and 2.5V libraries when tested to	Original	PDF