ATMEL 634
Abstract: ambit rev 4 LSI CMOS GATE ARRAY PO11V5 MH1099 MH1242 705uA
Text: Features • • • • • Up to 1.6 Million Used Gates and 596 Pads, with 3.3V, 3V, and 2.5V Libraries High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 Nominal System Level Integration Technology Cores on Request SRAM and TPRAM; Gate Level or Embedded
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5962-01B01
4138F
ATMEL 634
ambit rev 4
LSI CMOS GATE ARRAY
PO11V5
MH1099
MH1242
705uA
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AOI222
Abstract: AOI2223 AOI222H MH1099 MH1242 0.35-um CMOS standard cell library inverter
Text: Features • High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 Nominal • Up to 1.6 Million Used Gates and 596 Pads, with 3.3V, 3V, and 2.5V Libraries • System Level Integration Technology Cores on Request: SRAM and TRAM (Gate Level or Embedded) • I/O Interfaces:
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5962-01B01
4138E
AOI222
AOI2223
AOI222H
MH1099
MH1242
0.35-um CMOS standard cell library inverter
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AVR 8515 microcontroller datasheet
Abstract: Atmel 826 ATL35 ATMEL 222 32 bit risc processor using vhdl Atmel 542
Text: ATL35 GateArray/Embedded Array-1.4-03/02 ATL35 Gate Array/Embedded Array Description. 1-2 ATL35 Array Organization: Table . 1-2
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ATL35
AVR 8515 microcontroller datasheet
Atmel 826
ATMEL 222
32 bit risc processor using vhdl
Atmel 542
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AVR 8515 microcontroller
Abstract: FPGA AMI coding decoding tri state AOI222 AOI2223 AOI2223H AOI222H ATL35 0.35-um CMOS standard cell library inverter
Text: Features • System Level Integration Technology • 0.35 µm Geometry in Triple-level Metal • I/O Interfaces; CMOS, LVTTL, LVDS, PCI, USB – Output Currents up to 20 mA, 5V Tolerant I/O • Embedded Flash Memory with Capacities of 1Mbit, 2Mbit or 4Mbit
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22-bit
16-bit
1184B
03/00/xM
AVR 8515 microcontroller
FPGA AMI coding decoding
tri state
AOI222
AOI2223
AOI2223H
AOI222H
ATL35
0.35-um CMOS standard cell library inverter
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tristate buffer
Abstract: smd transistor AO HEX TO DECIMAL tristate buffer cmos A101 A201 MH1099E MH1156E PO11F MH1332E
Text: Features • High Speed - 180 ps Gate Delay - 2 Input NAND, FO = 2 nominal • Up to 1.198M Used Gates and 512 Pads with 3.3V, 3V and 2.5V Libraries when Tested to Space Quality Grades • Up to 1.6M Used Gates and 596 Pads with 3.3V, 3V and 2.5V Libraries when Tested to
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4110F
tristate buffer
smd transistor AO
HEX TO DECIMAL
tristate buffer cmos
A101
A201
MH1099E
MH1156E
PO11F
MH1332E
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54175
Abstract: PO11V5 16889 49035 56374 28548 58128 13.562 93408 atmel 246
Text: ERRATA SHEET DATE: April 2009 TO: Aerospace customers SUBJECT: 5V COMPLIANT BUFFERS WITH CORE POWERED AT 2.5V A 5V compliant buffer is a buffer powered by a 5V supply which is able to tolerate with negligible leakage current and without any reliability problems 5V signals (input buffer and pullup/pull-down) or drive 5V signals on its output (output buffer).
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125pf
130pf
135pf
140pf
145pf
150pf
155pf
160pf
165pf
170pf
54175
PO11V5
16889
49035
56374
28548
58128
13.562
93408
atmel 246
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Atmel 826
Abstract: atmel 952 Atmel 642 credence tester sbl 20100 atmel 530 dsp oak pine "VLSI TECHNOLOGY" ARM7TDMI DSP atmel 042 ATMEL 740
Text: ATL35 Series . Design Overview Table of Contents Section 1 ATL35 Series . 1-1
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ATL35
Atmel 826
atmel 952
Atmel 642
credence tester
sbl 20100
atmel 530
dsp oak pine
"VLSI TECHNOLOGY" ARM7TDMI DSP
atmel 042
ATMEL 740
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MH1099
Abstract: MH1242 PO11V5 4138G
Text: Features • • • • • Up to 1.6 Million Used Gates and 596 Pads, with 3.3V, 3V, and 2.5V Libraries High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 Nominal System Level Integration Technology Cores on Request SRAM and TRAM (Gate Level or Embedded)
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5962-01B01
4138G
MH1099
MH1242
PO11V5
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A101
Abstract: A201 MH1099E MH1156E MH1242E MH1332E AMI 1108
Text: Features • • • • • • • • • • • Up to 1.6M Used Gates and 596 Pads with 3.3V, 3V and 2.5V Libraries High Speed - 180 ps Gate Delay - 2 Input NAND, FO = 2 nominal System Level Integration Technology Cores on Request Memories: SRAM and TPRAM, Gate Level or Embedded, with EDAC
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20nts
4110H
A101
A201
MH1099E
MH1156E
MH1242E
MH1332E
AMI 1108
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A101
Abstract: A201 MH1099E MH1156E MH1242E MH1332E atmel 838 atmel edac dsp radiation hard
Text: Features • • • • • • • • • • • Up to 1.6M Used Gates and 596 Pads with 3.3V, 3V and 2.5V Libraries High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 nominal System Level Integration Technology Cores on Request Memories: SRAM and TPRAM, Gate Level or Embedded, with EDAC
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4110I
A101
A201
MH1099E
MH1156E
MH1242E
MH1332E
atmel 838
atmel edac
dsp radiation hard
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atmel 216
Abstract: ECL IC NAND CQFP 256 PIN actel Atmel 642 PO22 tri state ATL35 atmel 334 20PCI atmel h 952
Text: Features • High-speed - 150 ps Gate Delay - 2-input NAND, FO = 2 nominal • Up to 2.7 Million Used Gates and 976 Pins • System Level Integration Technology – Cores: ARM7TDMI and AVR RISC Microcontrollers, OakDSP™ and LodeDSPCores™, 10T/100 Ethernet MAC, USB and PCI Cores
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10T/100
ATL35
0802E
10/99/0M
atmel 216
ECL IC NAND
CQFP 256 PIN actel
Atmel 642
PO22
tri state
atmel 334
20PCI
atmel h 952
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1025460
Abstract: 7805 UA1044 UA1068 UA1084 UA1100 UA1120 UA1132 UA1144 UA1160
Text: Features • • • • • • • • • • • • • • • • • High performance ULC family suitable for large-sized CPLDs and FPGAs Conversion to 1,000,000 gates Pin counts to over 976 pins Any pin–out matched due to limited number of dedicated pads
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ATMEL 634
Abstract: ambit rev 4 C 828 dual mcga SRAM edac A101 A201 MH1099E MH1156E MH1242E
Text: Features • • • • • • • • • Up to 1.6M Used Gates and 596 Pads with 3.3V, 3V and 2.5V Libraries High Speed - 180 ps Gate Delay - 2 Input NAND, FO = 2 nominal System Level Integration Technology Cores on Request Memories: SRAM and TPRAM, Gate Level or Embedded, with EDAC
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4110G
ATMEL 634
ambit rev 4
C 828 dual
mcga
SRAM edac
A101
A201
MH1099E
MH1156E
MH1242E
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USD210
Abstract: USD228 USD256 USD312 USD384 USD432 USD492 USD594 USD700
Text: Features • • • • • • • • • • • • • • • • • • • • • • High-performance ULC Family Suitable for Large-sized CPLDs and FPGAs From 46K Gates up to 780K Gates Supported From 18 Kbit to 390 Kbit DPRAM Compatible with Xilinx or Altera
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4319B
USD210
USD228
USD256
USD312
USD384
USD432
USD492
USD594
USD700
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Untitled
Abstract: No abstract text available
Text: Features • • • • • • • • • • • • Up to 1.6M Used Gates and 596 Pads with 3.3V, 3V and 2.5V Libraries High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 nominal System Level Integration Technology Cores on Request Memories: SRAM and TPRAM, Gate Level or Embedded, with EDAC
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4110Lâ
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TEMIC PLD
Abstract: PRU10 PRD8 buffer 8x Structure of D flip-flop DFFSR AOI222 AOI2223 AOI2223H AOI222H MH1099
Text: MH1 1.6 Million gates Sea of Gates / Embedded Arrays 1. Description The MH1 Series Gate Array and Embedded Array families from TEMIC are fabricated in a 0.35µ CMOS process, with up to 3 levels of metal. This family features arrays with up to 1.6 million routable gates and 600 pins. The
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USD210
Abstract: USD228 USD256 USD312 USD384 USD432 USD492 USD594 USD700
Text: Features • • • • • • • • • • • • • • • • • • • • • • High-performance ULC Family Suitable for Large-sized CPLDs and FPGAs From 46K Gates up to 780K Gates Supported From 18 Kbit to 390 Kbit DPRAM Compatible with Xilinx or Altera
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4319C
USD210
USD228
USD256
USD312
USD384
USD432
USD492
USD594
USD700
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PO11V5
Abstract: No abstract text available
Text: Features • • • • • • • • • • • • • • • • • High performance ULC family suitable for large-sized CPLDs and FPGAs From 40K gates up to 780K gates supported Pin counts to over 976 pins Any pin–out matched due to limited number of dedicated pads
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4327D
PO11V5
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Untitled
Abstract: No abstract text available
Text: UA1 Series 0.35 µm ULC Series Description The UA1 series of ULCs is well suited for conversion large sized CPLDs and FPGAs. Devices are implemented in high–performance CMOS technology with 0.35–µ m drawn channel lengths, and are capable of supporting
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150ps
PO11V
PO11V5
325VDD
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4110L
Abstract: ATMEL 622 MH1RT QML A101 A201 MH1099E MH1156E MH1242E MH1332E
Text: Features • • • • • • • • • • • • Up to 1.6M Used Gates and 596 Pads with 3.3V, 3V and 2.5V Libraries High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 nominal System Level Integration Technology Cores on Request Memories: SRAM and TPRAM, Gate Level or Embedded, with EDAC
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4110L
ATMEL 622
MH1RT QML
A101
A201
MH1099E
MH1156E
MH1242E
MH1332E
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ATMEL 634
Abstract: MH1099 MH1242 PO11V5 dual lvds vhdl
Text: Features • • • • • Up to 1.6 Million Used Gates and 596 Pads, with 3.3V, 3V, and 2.5V Libraries High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 Nominal System Level Integration Technology Cores on Request SRAM and TRAM (Gate Level or Embedded)
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5962-01B01
4138G
ATMEL 634
MH1099
MH1242
PO11V5
dual lvds vhdl
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Untitled
Abstract: No abstract text available
Text: Features • • • • • Up to 1.6 Million Used Gates and 596 Pads, with 3.3V, 3V, and 2.5V Libraries High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 Nominal System Level Integration Technology Cores on Request SRAM and TRAM (Gate Level or Embedded)
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5962-01B01
4138Gâ
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A101
Abstract: A201 MH1099E MH1156E MH1242E MH1332E HEX TO DECIMAL ATMEL 220 dsp radiation hard
Text: Features • • • • • • • • • • • • Up to 1.6M Used Gates and 596 Pads with 3.3V, 3V and 2.5V Libraries High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 nominal System Level Integration Technology Cores on Request Memories: SRAM and TPRAM, Gate Level or Embedded, with EDAC
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4110K
A101
A201
MH1099E
MH1156E
MH1242E
MH1332E
HEX TO DECIMAL
ATMEL 220
dsp radiation hard
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UA1044
Abstract: UA1068 UA1084 UA1100 UA1120 UA1132 UA1144 UA1160 UA1184 UA1208
Text: UA1 Series 0.35 µm ULC Series Description The UA1 series of ULCs is well suited for conversion large sized CPLDs and FPGAs. Devices are implemented in high–performance CMOS technology with 0.35–µ m drawn channel lengths, and are capable of supporting
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150ps
PO11V
PO11V5
325VDD
UA1044
UA1068
UA1084
UA1100
UA1120
UA1132
UA1144
UA1160
UA1184
UA1208
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