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    dcfifo

    Abstract: asynchronous fifo vhdl altera MTBF dcfifo_mixed_widths
    Text: SCFIFO and DCFIFO Megafunctions UG-MFNALT_FIFO-6.2 User Guide Altera provides FIFO functions through the parameterizable single-clock FIFO SCFIFO and dual-clock FIFO (DCFIFO) megafunctions. The FIFO functions are mostly applied in data buffering applications that comply with the first-in-first-out


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    avalon verilog

    Abstract: vhdl code for branch metric unit vhdl code for traffic light control lanex branch metric unit VHDL design vhdl program for branch metric unit 8CRV
    Text: DesignCon 2010 Functional Verification of Highly Parameterizable IP and SystemLevel Design-Assembly Tools for FPGAs Jeffrey R. Fox, Altera Corporation jfox@altera.com Kent Orthner, Altera Corporation korthner@altera.com CP-01062-1.0 January 2010 Abstract Advances in verification technology for digital design, such as SystemVerilog Testbench


    Original     		PDF CP-01062-1 avalon verilog vhdl code for branch metric unit vhdl code for traffic light control lanex branch metric unit VHDL design vhdl program for branch metric unit 8CRV

    ENI 21

    Abstract: Parameterizable ic 7805 pin configuration temparature Sensors eni21 abb temperature Transmitter V1471 Type NMkk510,
    Text: Data Sheet 10/14 2.23 EN Parameterizable transmitter for frequency and rotational speed ENM 4 • Connects to – Active transmitters for rotational speed with AC voltage output: Type NMkk510, data sheet 10/14 2.16 Type NMk 611, data sheet 10/14 2.18 – Non contact, inductive pick up sensors for


    Original     		PDF NMkk510, ENI 21 Parameterizable ic 7805 pin configuration temparature Sensors eni21 abb temperature Transmitter V1471 Type NMkk510,

    Convolutional Encoder

    Abstract: ispLEVER project Navigator Convolutional encoder verilog coding Convolutional Puncturing Pattern digital clock project Convolutional decoder polynomial Viterbi Decoder ispLEVER project Navigator route place
    Text: Convolutional Encoder User’s Guide April 2003 ipug03_02 Lattice Semiconductor Convolutional Encoder User’s Guide Introduction Lattice’s Convolutional Encoder core is a parameterizable core for convolutional encoding of a continuous input data stream. The core allows variable code rates, constraint lengths and generator polynomials. The core also supports puncturing. Puncturing enables a large range of transmission rates and reduces the bandwidth requirement


    Original     		PDF ipug03 1-800-LATTICE Convolutional Encoder ispLEVER project Navigator Convolutional encoder verilog coding Convolutional Puncturing Pattern digital clock project Convolutional decoder polynomial Viterbi Decoder ispLEVER project Navigator route place

    ternary content addressable memory VHDL

    Abstract: tcam verilog code cam 128X48 AN8071
    Text: Using Memory in ispXPLD 5000MX Devices March 2005 Technical Note TN1030 Introduction This document describes memory usage and flow in the Lattice ispXPLD™ family of devices. A brief overview of the ispXPLD’s memory resources are presented along with the parameterizable memory elements supported by


    Original     		PDF 5000MX TN1030 1-800-LATTICE ternary content addressable memory VHDL tcam verilog code cam 128X48 AN8071

    Untitled

    Abstract: No abstract text available
    Text: LogiCORE IP Multi-Port Memory Controller v6.06.a DS643 February 22, 2013 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP Multi-Port Memory Controller (MPMC) is a fully parameterizable memory controller that supports SDRAM/DDR/DDR2/DDR3/LPDDR


    Original     		PDF DS643 PPC440MC)

    fir compiler v5

    Abstract: ds534 DSP48 SRL16 XIP162 matched filter matlab codes fir compiler xilinx digital FIR Filter using distributed arithmetic MATLAB code for halfband filter fir compiler v4
    Text: FIR Compiler v3.2 DS534 October 10, 2007 Product Specification Features General Description • Highly parameterizable drop-in module for Virtex , Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4, The Xilinx LogiCORE™ IP FIR Compiler core provides a common interface for users to generate highly parameterizable, area-efficient high-performance FIR filters


    Original     		PDF DS534 fir compiler v5 DSP48 SRL16 XIP162 matched filter matlab codes fir compiler xilinx digital FIR Filter using distributed arithmetic MATLAB code for halfband filter fir compiler v4

    ternary content addressable memory VHDL

    Abstract: ternary content addressable memory 128X48 AN8071 "Single-Port RAM" TCAM
    Text: Using Memory in ispXPLD 5000MX Devices January 2004 Technical Note TN1030 Introduction This document describes memory usage and flow in the Lattice ispXPLD™ family of devices. A brief overview of the ispXPLD’s memory resources are presented along with the parameterizable memory elements supported by


    Original     		PDF 5000MX TN1030 1-800-LATTICE ternary content addressable memory VHDL ternary content addressable memory 128X48 AN8071 "Single-Port RAM" TCAM

    EIA-IS103

    Abstract: two 4 bit binary multiplier Vhdl code verilog hdl code for 4 to 1 multiplexer in quartus 2 UG-01056-1
    Text: Megafunction Overview User Guide February 2009 UG-01056-1.0 Introduction Megafunctions are vendor-specific intellectual property IP blocks that are parameterizable and optimized for Altera device architectures. Altera provides a library of megafunctions,


    Original     		PDF UG-01056-1 EIA-IS103 two 4 bit binary multiplier Vhdl code verilog hdl code for 4 to 1 multiplexer in quartus 2

    UG-MF9304-3

    Abstract: EP2C5T144C6 integrated display device dual port memory cells AN550
    Text: ALTDQ and ALTDQS Megafunctions User Guide UG-MF9304-3.1 November 2009 Introduction The Quartus II software provides parameterizable megafunctions ranging from simple arithmetic units, such as adders and counters, to advanced phase-locked loop PLL blocks, multipliers, and memory structures. These megafunctions are


    Original     		PDF UG-MF9304-3 EP2C5T144C6 integrated display device dual port memory cells AN550

    1725E

    Abstract: No abstract text available
    Text: Features Compatible with an Embedded 32-bit ARM7TDMI Processor Up to 32 Programmable I/O Lines Two Peripherals per I/O Line Interrupt Generation on Event Glitch Filter Multi-driver Open Drain Option Certain Options Parameterizable on Request Number of Programmable Lines


    Original     		PDF 32-bit 32-bit 1725E

    serdes ip

    Abstract: 36b100 ORSO82G5 PI40 Parameterizable CSIX 15MULTICAST
    Text: CSIX-to-PI40 IP Core January 2004 IP Data Sheet • Ingress data Cframe FIFO size of 1,024 bytes. ■ Egress data Cframe FIFO size of 4,096 bytes. ■ Egress control Cframe FIFO size of 1,024 bytes. ■ Parameterizable PI40 user payload size 64, 72 or 80 octets and corresponding Cframe


    Original     		PDF CSIX-to-PI40 CSIX/PI40 CSIX-L1-to-PI40 ORSO82G5-2BM680. CSIX-PI40-O4-N1. serdes ip 36b100 ORSO82G5 PI40 Parameterizable CSIX 15MULTICAST

    AMBA APB

    Abstract: 1734B AMBA APB UART AMBA Peripheral Bus decoder data sheet AMBA peripheral bus AMBA APB spi
    Text: Features • • • • • • • • Compatible with an Embedded ARM7TDMI Processor Generates Transfers to/from Serial Peripherals Such as UART, USART, SSC and SPI Supports Up to 12 Peripherals – Parameterizable on Request One ARM Cycle Needed for a Transfer from Memory to Peripheral


    Original     		PDF 1734B AMBA APB AMBA APB UART AMBA Peripheral Bus decoder data sheet AMBA peripheral bus AMBA APB spi

    XAPP691

    Abstract: LocalLink XAPP258 10939 RAM32X1D vhdl code CRC 32 RAM64X1D XAPP261 SP006 xilinx logicore fifo generator 6.2
    Text: Application Note: Virtex-II and Virtex-II Pro Families R Parameterizable LocalLink FIFO Author: Wen Ying Wei, Dai Huang XAPP691 v1.0.1 May 10, 2007 Summary This application note describes the implementation of a parameterizable LocalLink FIFO, which is a First-In-First-Out memory queue with LocalLink interfaces on both sides. The LocalLink


    Original     		PDF XAPP691 XAPP258: XAPP261: SP006: DS232: XAPP691 LocalLink XAPP258 10939 RAM32X1D vhdl code CRC 32 RAM64X1D XAPP261 SP006 xilinx logicore fifo generator 6.2

    fir compiler v5

    Abstract: fir compiler xilinx XC6SLX150-2FGG484 Polyphase Filter Banks 90CLK fir compiler v4 digital FIR Filter VHDL code polyphase FIR filter interpolation matlaB simulink design FDATOOL verilog code for interpolation filter
    Text: FIR Compiler v5.0 DS534 June 24, 2009 Product Specification Introduction Overview The Xilinx LogiCORE IP FIR Compiler core provides a common interface for users to generate highly parameterizable, area-efficient high-performance FIR filters utilizing either Multiply-Accumulate MAC or


    Original     		PDF DS534 fir compiler v5 fir compiler xilinx XC6SLX150-2FGG484 Polyphase Filter Banks 90CLK fir compiler v4 digital FIR Filter VHDL code polyphase FIR filter interpolation matlaB simulink design FDATOOL verilog code for interpolation filter

    sample vhdl code for memory write

    Abstract: LFX1200B-05F900C RAM 1024x8
    Text: ispXPGA Memory Usage and Guidelines July 2002 Technical Note TN1028 Introduction This document describes memory usage flow in the ispXPGA family of devices. A brief overview of the ispXPGA memory resources is presented. The parameterizable memory elements built with configured sysMEM™ blocks


    Original     		PDF TN1028 d0000000100000001000000010 1-800-LATTICE sample vhdl code for memory write LFX1200B-05F900C RAM 1024x8

    ieee floating point multiplier vhdl

    Abstract: ieee floating point vhdl verilog code for floating point adder vhdl code for matrix multiplication vhdl code for inverse matrix vhdl 3*3 matrix vhdl code for N fraction Divider vhdl code of 32bit floating point adder vhdl code for floating point subtractor vhdl code for FFT 32 point
    Text: Floating-Point Megafunctions User Guide UG-01063-3.0 July 2010 This user guide provides information about the Altera floating-point megafunctions, which allow you to perform floating-point arithmetic in FPGAs through parameterizable functions that are optimized for Altera device architectures. You can


    Original     		PDF UG-01063-3 ieee floating point multiplier vhdl ieee floating point vhdl verilog code for floating point adder vhdl code for matrix multiplication vhdl code for inverse matrix vhdl 3*3 matrix vhdl code for N fraction Divider vhdl code of 32bit floating point adder vhdl code for floating point subtractor vhdl code for FFT 32 point

    CIC Compiler v1.0

    Abstract: cic filter cic compensation filters spartan 3a structure interpolation CIC Filter FPGA CIC Filter DSP48s DSP48 spartan 6 cic filters
    Text: CIC Compiler v1.0 DS613 October 10, 2007 Product Specification Features Applications • Parameterizable drop-in module for Virtex -5, Virtex-4, Virtex-II, Virtex-II Pro, Spartan™-3E, Spartan-3A, and Spartan-3A DSP devices • Channelization functions in a digital radio or


    Original     		PDF DS613 CIC Compiler v1.0 cic filter cic compensation filters spartan 3a structure interpolation CIC Filter FPGA CIC Filter DSP48s DSP48 spartan 6 cic filters

    UART usart

    Abstract: AMBA APB spi 1734A
    Text: Features • • • • • • • • Compatible with an Embedded ARM7TDMI Processor Generates Transfers to/from Serial Peripheral Such as UART, USART, SSC and SPI Supports Up to 12 Peripherals – Parameterizable on Request One ARM® Cycle Needed for a Transfer from Memory to Peripheral


    Original     		PDF 03/01/0M UART usart AMBA APB spi 1734A

    DDR2 phy

    Abstract: verilog hdl code for parity generator powerPC 440 schematics MT4HTF3264H ug406 PPC440MC VIRTEX-5 DDR2 sdram mig 3.61 LXT 971 VIRTEX-5 DDR PHY XAPP701
    Text: LogiCORE IP Multi-Port Memory Controller v6.06.a DS643 July 25, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP Multi-Port Memory Controller (MPMC) is a fully parameterizable memory controller that supports SDRAM/DDR/DDR2/DDR3/LPDDR


    Original     		PDF DS643 PPC440MC) DDR2 phy verilog hdl code for parity generator powerPC 440 schematics MT4HTF3264H ug406 PPC440MC VIRTEX-5 DDR2 sdram mig 3.61 LXT 971 VIRTEX-5 DDR PHY XAPP701

    Untitled

    Abstract: No abstract text available
    Text: ispLever CORE TM Viterbi Decoder User’s Guide October 2005 ipug04_02.0 Lattice Semiconductor Viterbi Decoder User’s Guide Introduction Lattice’s Viterbi Decoder core is a parameterizable core for decoding different combinations of convolutionally encoded sequences. The decoder core supports various code rates, constraint lengths and generator polynomials.


    Original     		PDF ipug04 LFX1200B, FE680,

    verilog code for fir filter using DA

    Abstract: vhdl code for FFT 4096 point P6421 p4826 vhdl code for radix 2-2 parallel FFT 16 point FIR FILTER implementation on fpga VHDL code for polyphase decimation filter FDATOOL DSP48 spartan 6 VHDL code for polyphase decimation filter using D
    Text: LogiCORE IP FIR Compiler v6.3 DS795 October 19, 2011 Product Specification Overview LogiCORE IP Facts The Xilinx LogiCORE IP FIR Compiler core provides a common interface for users to generate highly parameterizable, area-efficient high-performance FIR


    Original     		PDF DS795 ZynqTM-7000, verilog code for fir filter using DA vhdl code for FFT 4096 point P6421 p4826 vhdl code for radix 2-2 parallel FFT 16 point FIR FILTER implementation on fpga VHDL code for polyphase decimation filter FDATOOL DSP48 spartan 6 VHDL code for polyphase decimation filter using D

    DS643

    Abstract: microblaze locallink xilinx DDR3 controller user interface v605a B32R VIRTEX-5 DDR2 sdram mig 3.61 spartan6 mig ddr3 ddr3 ram slot pin detail 240 pin 0x000001DF verilog code for ddr2 sdram to virtex 5 using ip
    Text: LogiCORE IP Multi-Port Memory Controller v6.05.a DS643 October 19, 2011 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP Multi-Port Memory Controller (MPMC) is a fully parameterizable memory controller that supports SDRAM/DDR/DDR2/DDR3/LPDDR


    Original     		PDF DS643 PPC440MC) microblaze locallink xilinx DDR3 controller user interface v605a B32R VIRTEX-5 DDR2 sdram mig 3.61 spartan6 mig ddr3 ddr3 ram slot pin detail 240 pin 0x000001DF verilog code for ddr2 sdram to virtex 5 using ip

    Convolutional Encoder

    Abstract: CORE i3 block diagram CORE i3 timing diagram Convolutional core i5 Convolutional Puncturing Pattern polynomials LFX1200B OR4E02 V711
    Text: Convolutional Encoder March 2003 IP Data Sheet Features General Description • Parameterizable continuous convolutional encoder The top-level representation of the convolutional encoder is shown in Figure 1. For detailed signal descriptions, see Table 1.


    Original     		PDF