OPEN LVDS DESERIALIZATION IP Search Results

OPEN LVDS DESERIALIZATION IP Result Highlights (5)

Part	Manufacturer	Description
LBAA0QB1SJ-295	Murata Manufacturing Co Ltd	SX1262 MODULE WITH OPEN MCU
TCTH022BE	Toshiba Electronic Devices & Storage Corporation	Over Temperature Detection IC / VDD=1.7~5.5V / IPTCO=10μA / IDD=11.3μA / Open-drain type / FLAG signal latch function
TCTH021BE	Toshiba Electronic Devices & Storage Corporation	Over Temperature Detection IC / VDD=1.7~5.5V / IPTCO=10μA / IDD=11.3μA / Open-drain type
TCTH012BE	Toshiba Electronic Devices & Storage Corporation	Over Temperature Detection IC / VDD=1.7~5.5V / IPTCO=1μA / IDD=1.8μA / Open-drain type / FLAG signal latch function
TCTH011BE	Toshiba Electronic Devices & Storage Corporation	Over Temperature Detection IC / VDD=1.7~5.5V / IPTCO=1μA / IDD=1.8μA / Open-drain type

OPEN LVDS DESERIALIZATION IP Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
JC42 Abstract: P802 SSTL-18 intel 956 motherboard CIRCUIT diagram PCI SIZE 10gbps serdes Text: Section III. I/O Standards This section provides information on Stratix single-ended, voltagereferenced, and differential I/O standards. It contains the following chapters: Revision History • Chapter 4, Selectable I/O Standards in Stratix & Stratix GX Devices	Original		PDF
Untitled Abstract: No abstract text available Text: RapidIO 8-bit Port Physical Layer Interface June 7, 2001 Product Specification LogiCORE Facts Resources Used Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-559-7114 URL: www.xilinx.com/ipcenter Support: support.xilinx.com	Original		PDF
2258J Abstract: open LVDS deserialization IP JB 2256 Text: PRELIMINARY SPECIFICATION > 4 M C SO N E T/SD H /A TM OC-48 1 :8 RECEIVER FEATURES • Micro-power Bipolar technology • Complies with ANSI, Bellcore, and ITU-T specifications • Supports 2.4 Gbps OC-48 • 8-bit LVDS data path • Compact 100 TQFP/TEP package	OCR Scan	S3042 OC-48 OC-48) S3042 OC-48 2258J open LVDS deserialization IP JB 2256	PDF
Untitled Abstract: No abstract text available Text: 19-2864; Rev 4; 3/05 Programmable DC-Balance 21-Bit Deserializers The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/ MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a separate supply, allowing 1.8V to 5V output logic levels.	Original	21-Bit MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/ MAX9222 MAX9209/MAX9211/MAX9213/ MAX9215 MAX9210/MAX9212/MAX9214/MAX9216 D222EUM MAX9220EUM	PDF
Untitled Abstract: No abstract text available Text: 2013.10.17 AN-518 SGMII Interface Implementation Using Soft CDR Mode of Altera FPGAs Subscribe Send Feedback The Serial Gigabit Media Independent Interface SGMII protocol provides connectivity between the physical layer (PHY) and the Ethernet media controller (MAC). The SGMII solution for Altera FPGAs allows you	Original	AN-518	PDF
oc-192 serdes Abstract: history of automatic phase selector TRANSISTOR D123 JC42 P802 SSTL-18 Compact PCI Backplane Block Diagram Altera source-synchronous Text: Section IV. I/O Standards This section provides information about the I/O standards and interfaces for Stratix and Stratix GX devices. This section includes the following chapters: Revision History • Chapter 16, Selectable I/O Standards in Stratix & Stratix GX Devices	Original	125-Gbps oc-192 serdes history of automatic phase selector TRANSISTOR D123 JC42 P802 SSTL-18 Compact PCI Backplane Block Diagram Altera source-synchronous	PDF
verilog code to generate sine wave Abstract: open LVDS deserialization IP verilog code for sine wave using FPGA 0x0000011 C71B MB86064 fujitsu lvds standard BF15 D132 LVDS17 Text: High-Speed Data Interface for Stratix Devices & Fujitsu MB86064 DACs Application Note AN-316-1.0 Introduction Implementing the digital interface to drive a high-speed digital-toanalogue converter DAC is challenging. The conversion rates of highspeed DACs has increased significantly in recent years, so special design	Original	MB86064 AN-316-1 14-bit verilog code to generate sine wave open LVDS deserialization IP verilog code for sine wave using FPGA 0x0000011 C71B fujitsu lvds standard BF15 D132 LVDS17	PDF
open LVDS deserialization IP Abstract: DS243 crc verilog code 16 bit RAPIDIO Text: RapidIO 8-bit Port Physical Layer v3.0.2 DS243 February 10, 2005 Product Specification Introduction LogiCORE Facts The LogiCORE RapidIO Physical Layer Interface, a fixed-netlist solution for the RapidIO interconnect, is a pre-implemented and fully tested module for Xilinx	Original	DS243 2V1000FF896-4 2V2000FF896-4 2VP7FF896-5 2VP20F896modules open LVDS deserialization IP crc verilog code 16 bit RAPIDIO	PDF
EP2AGX45 Abstract: DDR3 jedec EP2AGX260 EP2AGX45 ubga RSDS receiver altLVDS EIA-644 SSTL-15 SSTL-18 1152-pin Text: Section II. I/O Interfaces This section provides information on Arria II GX device I/O features, external memory interfaces, and high-speed differential interfaces with DPA. This section includes the following chapters: • Chapter 6, I/O Features in Arria II GX Devices	Original		PDF
lpddr2 datasheet Abstract: lpddr2 UniPHY lpddr2 Datasheet LPDDR2 SDRAM jesd79-3d HSUL-12 lpddr2 phy lpddr2 DQ calibration Dual LPDDR2 Datasheet LPDDR2 Text: Section II. I/O Interfaces This section provides information about Stratix V device I/O features, external memory interfaces, and high-speed differential interfaces with dynamic phase alignment DPA . This section includes the following chapters: • Chapter 5, I/O Features in Stratix V Devices	Original		PDF
hf1932 Abstract: HSUL-12 DDR3U DIODE CQ 618 lvds cable 20 pins rf1517 UniPHY lpddr2 SSTL-135 Text: Section II. I/O Interfaces This section provides information about Stratix V device I/O features, external memory interfaces, and high-speed differential interfaces with dynamic phase alignment DPA . This section includes the following chapters: • Chapter 5, I/O Features in Stratix V Devices	Original		PDF
sdc 606 Abstract: EP4GX230KF40C2 EP3SL150F1152C2 hsmc connector altera SOP top marking Stratix II GX FPGA Development Board Reference Manual Text: AN 606: POS-PHY Level 4 SPI-4.2 Loopback Reference Design AN-606-1.0 May 2010 The packet over SONET/SDH physical layer (POS-PHY) Level 4—Phase 2 (SPI-4.2) loopback reference design shows how you can transmit and receive data using the Altera POS-PHY Level 4 MegaCore® function and the Stratix® IV and Stratix III	Original	AN-606-1 sdc 606 EP4GX230KF40C2 EP3SL150F1152C2 hsmc connector altera SOP top marking Stratix II GX FPGA Development Board Reference Manual	PDF
verilog code for UART with BIST capability Abstract: vhdl code for 8 to 3 encoder using concurrent sta 2 port register file open LVDS deserialization IP OC768 ARM10 ARM946 SR40 TLK2201 verilog code for ahb bus slave Text: SR40 0.095-µm High-Speed Copper Standard Cell/Gate Array ASIC Version 1.1 May 17, 2001 Copyright  Texas Instruments Incorporated, 2001 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the	Original	24-hour verilog code for UART with BIST capability vhdl code for 8 to 3 encoder using concurrent sta 2 port register file open LVDS deserialization IP OC768 ARM10 ARM946 SR40 TLK2201 verilog code for ahb bus slave	PDF
altera marking Code Formats Cyclone 2 Abstract: verilog code for spi4.2 to fifo vhdl 4-bit binary calculator cyclone FPGA 144 EP3C40F780C6 EP4SGX230DF29C3ES EP4SGX70 PM3388 EP3SE50F780 OIF-SPI4-02 Text: POS-PHY Level 4 MegaCore Function User Guide POS-PHY Level 4 MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com UG-IPPOSPHY4-10.0 Document last updated for Altera Complete Design Suite version: Document publication date: 10.0	Original	UG-IPPOSPHY4-10 altera marking Code Formats Cyclone 2 verilog code for spi4.2 to fifo vhdl 4-bit binary calculator cyclone FPGA 144 EP3C40F780C6 EP4SGX230DF29C3ES EP4SGX70 PM3388 EP3SE50F780 OIF-SPI4-02	PDF

mercury motherboards regulator ic Abstract: TRANSISTOR SUBSTITUTION DATA BOOK 1993 CORDIC to generate sine wave fpga verilog code for CORDIC to generate sine wave verilog code for cdma transmitter vhdl code for cordic intel atom microprocessor verilog code for 2D linear convolution filtering mercury computer motherboard sumida inverter IV Text: Stratix Device Handbook, Volume 2 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com S5V2-3.5 Copyright 2006 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and	Original	EL7551C EL7564C EL7556BC EL7562C EL7563C mercury motherboards regulator ic TRANSISTOR SUBSTITUTION DATA BOOK 1993 CORDIC to generate sine wave fpga verilog code for CORDIC to generate sine wave verilog code for cdma transmitter vhdl code for cordic intel atom microprocessor verilog code for 2D linear convolution filtering mercury computer motherboard sumida inverter IV	PDF
RSDS Abstract: DDR3 jedec EIA-644 SSTL-15 SSTL-18 1932-pin Text: Section II. I/O Interfaces This section provides information on Stratix IV device I/O features, external memory interfaces, and high-speed differential interfaces with DPA. This section includes the following chapters: • Chapter 6, I/O Features in Stratix IV Devices	Original		PDF
CTXIL206 Abstract: vhdl code for multiplexing MPEG2 sd card interfacing spartan 3E FPGA RX 3E vhdl code for multiplexing table dvb-t XAPP1015 vhdl code for spartan 6 audio vhdl code for multiplexing Tables in dvb-t vhdl code for dvb-t 2 YCbCr output LVDS Text: Audio/Video Connectivity Solutions for Spartan-3E FPGAs Reference Designs for the Broadcast the Broadcast Industry: Volume 3 Industry: Volume 3 [optional] XAPP1015 v1.0 September 28, 2009 [optional] Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development	Original	XAPP1015 CTXIL206 vhdl code for multiplexing MPEG2 sd card interfacing spartan 3E FPGA RX 3E vhdl code for multiplexing table dvb-t XAPP1015 vhdl code for spartan 6 audio vhdl code for multiplexing Tables in dvb-t vhdl code for dvb-t 2 YCbCr output LVDS	PDF
EP3SE50 Abstract: SSTL-15 texas instruments handbook EIA-644 SSTL-18 alt_iobuf Text: Section II. I/O Interfaces This section provides information on Stratix III device I/O features, external memory interfaces, and high-speed differential interfaces with DPA. This section includes the following chapters: • Chapter 7, Stratix III Device I/O Features	Original		PDF
texas instruments handbook Abstract: handbook texas instruments SSTL-15 texas instruments the voltage regulator handbook EIA-644 SSTL-18 HSTL standards Text: Section II. I/O Interfaces This section provides information on Stratix III device I/O features, external memory interfaces, and high-speed differential interfaces with DPA. This section includes the following chapters: Revision History Altera Corporation	Original		PDF
serdes hdmi optical fibre Abstract: camera-link to hd-SDI converter RS-485 spice camera-link to HDMI converter 10G BERT 40 pin lvds laptop connector camera-link to 3G-SDI converter hd-SDI deserializer LVDS HDMI cat5 specifications of tdr Text: LVDS Owner’s Manual Including High-Speed CML and Signal Conditioning Fourth Edition 2008 High-Speed Interface Technologies Overview. 9-13 Network Topology. 15-17 SerDes Architectures. 19-29 Termination and Translation.31-38	Original		PDF
Untitled Abstract: No abstract text available Text: APEX II April 2001, ver. 1.0 Features. Data Sheet • Preliminary Information ■ ■ Altera Corporation A-DS-APEXII-1.0 Programmable Logic Device Family Programmable logic device PLD manufactured using a 0.15-µm alllayer copper-metal fabrication process (up to eight layers of metal)	Original		PDF
lattice maco Abstract: No abstract text available Text: LatticeSC MACO Core LSCDR1X18 Low-Speed Clock and Data Recovery User’s Guide January 2008 Technical Note TN1122 Introduction The LatticeSC LSCDR low-speed clock and data recovery MACO™ core is a fully integrated low-power clock and data recovery (CDR) block designed for low-speed serial communication systems. The clock and data recovery circuit (CDR) is a digital base band circuit that post-processes a binary signal to produce an optimally sampled	Original	LSCDR1X18 TN1122 LSCDR1X18 500Mbps. 1-800-LATTICE LatticeSCM115. lattice maco	PDF
vhdl source code for i2c optic Abstract: IPC-2141 TZA3015HW william orr tza3015 register electronica digital RF transmitter dr1 CLK180 XAPP265 XAPP268 Text: Application Note: Virtex-II and Virtex-II Pro Families Connecting Xilinx FPGAs to the Philips A-rate Fibre Optic Transceiver R XAPP764 v1.0 May 25, 2004 Summary This application note shows how a Xilinx Virtex -II or Virtex-II Pro™ device can connect to a	Original	XAPP764 TZA3015HW TZA3015HW. TZA3015HW 0-13-084408-x) vhdl source code for i2c optic IPC-2141 william orr tza3015 register electronica digital RF transmitter dr1 CLK180 XAPP265 XAPP268	PDF
424M Abstract: LMH0041 LMH0051 LMH0071 LMH0341 open LVDS deserialization IP Text: November 1, 2010 3 Gbps, HD, SD, DVB-ASI SDI Deserializer with Loopthrough and LVDS Interface General Description Key Specifications The LMH0341/0041/0071/0051 SDI Deserializers are part of National’s family of FPGA-Attach SER/DES products supporting 5-bit LVDS interfaces with FPGAs. When paired with	Original	LMH0341/0041/0071/0051 LMH0341 424M LMH0041 LMH0051 LMH0071 open LVDS deserialization IP	PDF

OPEN LVDS DESERIALIZATION IP Search Results

OPEN LVDS DESERIALIZATION IP Result Highlights (5)

OPEN LVDS DESERIALIZATION IP Datasheets Context Search

JC42

Untitled

2258J

Untitled

Untitled

oc-192 serdes

verilog code to generate sine wave

open LVDS deserialization IP

EP2AGX45

lpddr2 datasheet

hf1932

sdc 606

verilog code for UART with BIST capability

altera marking Code Formats Cyclone 2

mercury motherboards regulator ic

RSDS

CTXIL206

EP3SE50

texas instruments handbook

serdes hdmi optical fibre

Untitled

lattice maco

vhdl source code for i2c optic

424M