NANYA LPDDR2 SPEC Search Results

NANYA LPDDR2 SPEC Result Highlights (5)

Part	ECAD Model	Manufacturer	Description	Download	Buy
MQ80960MC-25/B-SPECIAL		Rochester Electronics LLC	80960MC - 32-Bit Microprocessor With Floating Point Unit and MMU (Special)
9513ADC-SPECIAL		Rochester Electronics LLC	9513A - Rochester Manufactured 9513, System Timing Controller
MSPEC2L0B5010		Amphenol Communications Solutions	SPE Cable Assembly, IP20 Plug to IP20 Plug, 0.5m
MSPEC6P2AE010		Amphenol Communications Solutions	SPE IP67 Cable Assembly, IP67 Plug on one end and Pigtail on other end, 5.0m
MSPEC2L0B3010		Amphenol Communications Solutions	Single Pair Ethernet cable assemblies IP20 plug both end, MSPE series

NANYA LPDDR2 SPEC Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
hynix lpddr2 Abstract: ELPIDA mobile dram LPDDR2 Elpida LPDDR2 Memory hynix lpddr2 sdram lpddr2 DQ calibration Hynix 4Gb LPDDR2 LPDDR2 SDRAM hynix NT6TL64M32AQ -G1 lpddr2-s2 LPDDR2 1Gb Memory Text: 2Gb LPDDR2-S4 SDRAM NT6TL64M32AQ Feature Options  Double-data rate architecture; two data transfer per clock cycle  Bidirectional, data strobe DQS, /DQS is transmitted/received with data, to be used in capturing data at the receiver  Differential clock inputs (CK and /CK)	Original	NT6TL64M32AQ -64Meg 64M32 -168-ball hynix lpddr2 ELPIDA mobile dram LPDDR2 Elpida LPDDR2 Memory hynix lpddr2 sdram lpddr2 DQ calibration Hynix 4Gb LPDDR2 LPDDR2 SDRAM hynix NT6TL64M32AQ -G1 lpddr2-s2 LPDDR2 1Gb Memory	PDF
NT6SM16M16AG-S1 Abstract: lpddr2-s2 NT6SM16M16AG NT6SM16M16AG-S1I 128T64 Text: 256Mb LPSDR SDRAM NT6SM16M16AG NT6SM8M32AK Feature Options Fully synchronous; all signals registered on positive edge of z z Marking VDD /VDDQ system clock -1.8V/1.8V M Internal, pipelined operation; column address can be changed z z every clock cycle	Original	256Mb NT6SM16M16AG NT6SM8M32AK -16Meg -54-ball -90-ball x13mm) 16M16 NT6SM16M16AG-S1 lpddr2-s2 NT6SM16M16AG-S1I 128T64	PDF
A1930 Abstract: No abstract text available Text: 256Mb LPSDR SDRAM NT6SM8M32AK Feature  Options Fully synchronous; all signals registered on positive edge of Marking  VDD /VDDQ system clock -1.8V/1.8V  M Internal, pipelined operation; column address can be changed  Configuration every clock cycle	Original	256Mb NT6SM8M32AK -16Meg 16M16 A1930	PDF
Lpddr2 Idd7 Abstract: 216-ball LPDDR2 NT6SM16M32 NT6SM16M32AK-S1 Text: 512Mb LPSDR SDRAM NT6SM16M32AK Feature  Options Fully synchronous; all signals registered on positive edge of Marking  VDD /VDDQ system clock -1.8V/1.8V  M Internal, pipelined operation; column address can be changed  Configuration every clock cycle	Original	512Mb NT6SM16M32AK -16Meg -90-ball x13mm) 16M32 Lpddr2 Idd7 216-ball LPDDR2 NT6SM16M32 NT6SM16M32AK-S1	PDF
NT6SM32M16AG-S1 Abstract: NT6SM16M32 128M32 NT6SM16M32AK NT6SM32M16AG Lpddr2 Idd1 8M32R NT6SM16M32AK-S1 lpddr2 layout lpddr2 256mb Text: 512Mb LPSDR SDRAM NT6SM32M16AG / NT6SM16M32AK / NT6SM16M32RAK Feature  Options Fully synchronous; all signals registered on positive edge of  Marking VDD /VDDQ system clock -1.8V/1.8V  M Internal, pipelined operation; column address can be changed	Original	512Mb NT6SM32M16AG NT6SM16M32AK NT6SM16M32RAK -32Meg -16Meg -54-ball -90-ball x13mm) 32M16 NT6SM32M16AG-S1 NT6SM16M32 128M32 Lpddr2 Idd1 8M32R NT6SM16M32AK-S1 lpddr2 layout lpddr2 256mb	PDF
Lpddr2 Idd7 Abstract: COMMAND42 lpddr2 256mb lpddr2 layout NT6SM32M16AG-S2 LPDDR2 1Gb Memory NT6SM16M32 Text: 512Mb LPSDR SDRAM NT6SM32M16AG / NT6SM16M32AK / NT6SM16M32RAK Feature  Options Fully synchronous; all signals registered on positive edge of Marking  VDD /VDDQ system clock -1.8V/1.8V  M Internal, pipelined operation; column address can be changed	Original	512Mb NT6SM32M16AG NT6SM16M32AK NT6SM16M32RAK -32Meg -16Meg -54-ball -90-ball x13mm) 32M16 Lpddr2 Idd7 COMMAND42 lpddr2 256mb lpddr2 layout NT6SM32M16AG-S2 LPDDR2 1Gb Memory NT6SM16M32	PDF
Lpddr2 Idd7 Abstract: Jedec lpddr2 216-ball LPDDR 8Gb lpddr2-s2 Text: 256Mb LPSDR SDRAM NT6SM8M32AK Feature  Options Fully synchronous; all signals registered on positive edge of Marking  VDD /VDDQ system clock -1.8V/1.8V  M Internal, pipelined operation; column address can be changed  Configuration every clock cycle	Original	256Mb NT6SM8M32AK -16Meg -54-ball -90-ball x13mm) 16M16 Lpddr2 Idd7 Jedec lpddr2 216-ball LPDDR 8Gb lpddr2-s2	PDF
NTC 200-9 Abstract: a2240 128M16 A1930 NT6SM16M32 Text: 512Mb LPSDR SDRAM NT6SM16M32AK Feature  Options Fully synchronous; all signals registered on positive edge of Marking  VDD /VDDQ system clock -1.8V/1.8V  M Internal, pipelined operation; column address can be changed  Configuration every clock cycle	Original	512Mb NT6SM16M32AK -16Meg 16M32 NTC 200-9 a2240 128M16 A1930 NT6SM16M32	PDF
NT6DM16M16AD-T1 Abstract: 64M32 HP 3458 NT6DM16M16AD-T1I Text: 256Mb LPDDR SDRAM NT6DM16M16AD / NT6DM8M32AC Options Feature  Double-data rate architecture; two data transfer per clock cycle  Bidirectional, data strobe DQS is transmitted/received with data, to be used in capturing data at the receiver Marking  VDD /VDDQ	Original	256Mb NT6DM16M16AD NT6DM8M32AC -16Meg 16M16 NT6DM16M16AD-T1 64M32 HP 3458 NT6DM16M16AD-T1I	PDF
lpddr2 256mb Abstract: NT6DM8M32AC-T1 NT6DM16M16AD NT6DM8M32AC lpddr2 layout NT6DM8M32 Dual LPDDR2 lpddr2 256mb kgd lpddr2-s2 Text: 256Mb LPDDR SDRAM NT6DM16M16AD / NT6DM8M32AC Options Feature  Double-data rate architecture; two data transfer per clock cycle  Bidirectional, data strobe DQS is transmitted/received with data, to be used in capturing data at the receiver Marking  VDD /VDDQ	Original	256Mb NT6DM16M16AD NT6DM8M32AC -16Meg 16M16 lpddr2 256mb NT6DM8M32AC-T1 NT6DM8M32AC lpddr2 layout NT6DM8M32 Dual LPDDR2 lpddr2 256mb kgd lpddr2-s2	PDF
Untitled Abstract: No abstract text available Text: 256Mb LPDDR SDRAM NT6DM16M16AD / NT6DM8M32AC Options Feature  Double-data rate architecture; two data transfer per clock cycle  Bidirectional, data strobe DQS is transmitted/received with data, to be used in capturing data at the receiver  Differential clock inputs (CK and /CK)	Original	256Mb NT6DM16M16AD NT6DM8M32AC -16Meg 16M16	PDF
NT6DM16M Abstract: No abstract text available Text: 512Mb LPDDR SDRAM NT6DM32M16AD / NT6DM16M32AC Feature Options  Double-data rate architecture; two data transfer per clock cycle  Bidirectional, data strobe DQS is transmitted/received with Marking  VDD /VDDQ -1.8V/1.8V M data, to be used in capturing data at the receiver	Original	512Mb NT6DM32M16AD NT6DM16M32AC -32Meg 32M16 -16Meg 16M32 NT6DM16M	PDF
NT6DM32M16AD-T1 Abstract: NT6DM32M16AD NT6DM16M32AC-T1 NT6DM16M32AC NT6DM16M32AC-T3 216-ball NT6DM32M16AD-T3 256M16 lpddr2 256mb lpddr2 layout Text: 512Mb LPDDR SDRAM NT6DM32M16AD / NT6DM16M32AC Feature Options  Double-data rate architecture; two data transfer per clock cycle  Bidirectional, data strobe DQS is transmitted/received with Marking  VDD /VDDQ -1.8V/1.8V M data, to be used in capturing data at the receiver	Original	512Mb NT6DM32M16AD NT6DM16M32AC -32Meg -16Meg -60-ball -90-ball NT6DM32M16AD-T1 NT6DM16M32AC-T1 NT6DM16M32AC NT6DM16M32AC-T3 216-ball NT6DM32M16AD-T3 256M16 lpddr2 256mb lpddr2 layout	PDF
LPDDR 8Gb Abstract: lpddr2 256mb NT6DM32M16AD-T1 NT6DM32M16AD nanya lpddr2 spec Text: 512Mb LPDDR SDRAM NT6DM32M16AD / NT6DM16M32AC Feature Options  Double-data rate architecture; two data transfer per clock cycle  Bidirectional, data strobe DQS is transmitted/received with Marking  VDD /VDDQ -1.8V/1.8V M data, to be used in capturing data at the receiver	Original	512Mb NT6DM32M16AD NT6DM16M32AC -32Meg -16Meg -60-ball -90-ball LPDDR 8Gb lpddr2 256mb NT6DM32M16AD-T1 nanya lpddr2 spec	PDF

NT6TL32M Abstract: No abstract text available Text: 512Mb LPDDR2-S4 SDRAM NT6TL16M32AQ/ NT6TL32M16AQ Feature  Double-data rate architecture; two data transfer per clock cycle  Bidirectional, data strobe DQS,  is transmitted/received with data, to be used in capturing data at the receiver 	Original	512Mb NT6TL16M32AQ/ NT6TL32M16AQ NT6TL32M	PDF
NT6TL128M32AQ-G1 Abstract: NT6TL256T32 NT6TL256T32AQ-G1 NT6TL128M32AQ-G0 NT6TL128M32 hynix lpddr2 NT6TL128T64AR-G0 NT6TL256 NT6TL128T64AR-G1I NT6TL256T32AQ-G2 Text: 4Gb/8Gb LPDDR2-S4 SDRAM NT6TL128M32AI Q /NT6TL256T32AQ NT6TL256T32AS/NT6TL128T64AR(3/5) Feature  Double-data rate architecture; two data transfer per clock cycle  Bidirectional, data strobe (DQS, ) is transmitted/received with data, to be used in capturing data at the receiver	Original	NT6TL128M32AI /NT6TL256T32AQ NT6TL256T32AS/NT6TL128T64AR NT6TL128M32AQ-G1 NT6TL256T32 NT6TL256T32AQ-G1 NT6TL128M32AQ-G0 NT6TL128M32 hynix lpddr2 NT6TL128T64AR-G0 NT6TL256 NT6TL128T64AR-G1I NT6TL256T32AQ-G2	PDF
NT6TL256T32AQ Abstract: NT6TL128M32AI hynix lpddr2 NT6TL128M32AQ-G1 LPDDR2 1Gb Memory NT6TL128M32 Hynix 4Gb LPDDR2 NT6TL256T32AQ-G1 NT6TL128M32AQ-G0 Elpida LPDDR2 Memory Text: 4Gb/8Gb LPDDR2-S4 SDRAM NT6TL128M32AI Q /NT6TL256T32AQ NT6TL256T32AS/NT6TL128T64AR(3/5) Feature  Double-data rate architecture; two data transfer per clock cycle  Bidirectional, data strobe (DQS, ) is transmitted/received with data, to be used in capturing data at the receiver	Original	NT6TL128M32AI /NT6TL256T32AQ NT6TL256T32AS/NT6TL128T64AR NT6TL256T32AQ hynix lpddr2 NT6TL128M32AQ-G1 LPDDR2 1Gb Memory NT6TL128M32 Hynix 4Gb LPDDR2 NT6TL256T32AQ-G1 NT6TL128M32AQ-G0 Elpida LPDDR2 Memory	PDF