Contextual Info: R /lin S n M I ii^ n w r « MT9D136; W1T18D236 t MEGr 2 MEG x 36 DRAM MODULE 1 MEG, 2 MEG X 36 DRAM MODULE FAST PAGE MODE FEATURES • Common RAS control per side pinout in a 72-pin, single-in-line memory module • High-performance CMOS silicon-gate process.

U15-U10

Abstract: MT18D236
Contextual Info: MT9D136, MT18D236 1 MEG. 2 MEG x 36 DRAM MODULE |V /|ICZRO N DRAM MODULE 1 MEG, 2 MEG x 36 FEATURES PIN ASSIGNMENT Front View • C o m m o n R A S co n tro l p er sid e p in o u t in a 72-p in , sin g le-in -lin e m em o ry m o d u le (SIM M ) • H ig h -p e rfo rm a n ce C M O S silico n -g a te p ro cess.

MT18D236

Contextual Info: DRAM MODULE 1 MEG, 2 MEG x 36 4, 8 MEGABYTE, 5V 4 ,8ME GABY TE’5VFAST PAGE MODE FEATURES PIN ASSIGNMENT Front View • Common RAS control per side pinout in a 72-pin, single-in-line m emory module (SIMM) • High-performance CM OS silicon-gate process.

MT9D136G-6

Contextual Info: |U|IC=RON 1 MEG DRAM MODULE X MT9D136 36 DRAM MODULE 1 MEG x 36 DRAM FAST-PAGE-MODE FEATURES • Common RAS control pinout in a 72-pin single-in-line package • High-performance CMOS silicon-gate process. • Single 5V ±10% power supply • All device pins are TTL-compatible

Contextual Info: MICR ON S E M I C O N D U C T O R INC m i c r o b l l l S M T G D Q 6 1 3 H 152 M U R N b3E T> n 1 MEG 1 MEG DRAM MODULE X MT9D136 36 DRAM MODULE X 36 DRAM FAST-PAGE-MODE FEATURES PIN ASSIGNMENT Top View • Common RAS control pinout in a 72-pin single-in-line

Contextual Info: p ilC R O N 1 MEG X MT9D136 36 DRAM MODULE 1 MEG x 36 DRAM DRAM MODULE FAST PAGE MODE FEATURES PIN ASSIGNMENT Top View OPTIONS 72-Pin SIMM (T -1 1 ) M T9D 136M G ImTiTrn'nTTriïïm iTïïïïiTiriïm „ [rrrrmmiTrrrmmffiTnTnTrrm MARKING • Timing 60ns access

MT9D136

Contextual Info: |U|IC=RO N 1 MEG DRAM MODULE X MT9D136 36 DRAM M ODULE 1 MEG x 36 DRAM FAST-PAGE-MODE FEATURES PIN ASSIGNMENT Top View • Common RAS control pinout in a 72-pin single-in-line package • High-perform ance CM OS silicon-gate process. • Single 5V +10% power supply