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STMicroelectronics RHFLVDS218K1 Rad-Hard Low Voltage Differential Signaling Deserializer CMOS/TTL 21-Bit 3V to 3.6V Gold 48-Pin Flat SMD Strip Pack (Alt: RHFLVDS218K1)
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Avnet Americas	RHFLVDS218K1		15		5	1 - 10 - 100 - 1000 - 10000 -	Get Quote

LVDS218 Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
Untitled Abstract: No abstract text available Text: Standard Products LVDS218 Deserializer Data Sheet August 14, 2002 FEATURES INTRODUCTION q q q q q q q q q q q q The LVDS218 Deserializer converts the three LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 50MHz, 21 bits of TTL data are transmitted at a	Original	PDF	UT54LVDS218 50MHz MIL-STD-883 50MHz, 48-lead
Untitled Abstract: No abstract text available Text: Standard Products LVDS218 Deserializer Data Sheet June 24, 2002 FEATURES INTRODUCTION q q q q q 15 to 50MHz shift clock support 50% duty cycle on receiver output clock Low power consumption Cold sparing all pins Power-down mode <200µW max The LVDS218 Deserializer converts the three LVDS data	Original	PDF	UT54LVDS218 50MHz 50MHz, 48-lead
Untitled Abstract: No abstract text available Text: Standard Products LVDS218 Deserializer Data Sheet December, 2008 FEATURES INTRODUCTION ̌ ̌ ̌ ̌ ̌ ̌ ̌ ̌ ̌ ̌ ̌ ̌ The LVDS218 Deserializer converts the three LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 75MHz, 21 bits of TTL data are transmitted at a	Original	PDF	UT54LVDS218 75MHz, 525Mbps 75MHz
UT54LVDS218 Abstract: No abstract text available Text: Standard Products LVDS218 Deserializer Data Sheet October 28, 2008 FEATURES INTRODUCTION The LVDS218 Deserializer converts the three LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 75MHz, 21 bits of TTL data are transmitted at a	Original	PDF	UT54LVDS218 75MHz MIL-STD-883 48-lead
Untitled Abstract: No abstract text available Text: Standard Products LVDS218 Deserializer Data Sheet September, 2006 FEATURES INTRODUCTION The LVDS218 Deserializer converts the three LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 75MHz, 21 bits of TTL data are transmitted at a	Original	PDF	UT54LVDS218 75MHz MIL-STD-883 48-lead
LVDS218 Abstract: No abstract text available Text: Standard Products LVDS218 Deserializer Data Sheet September 2002 FEATURES INTRODUCTION q q q q q q q q q q q q The LVDS218 Deserializer converts the three LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 50MHz, 21 bits of TTL data are transmitted at a	Original	PDF	UT54LVDS218 50MHz MIL-STD-883 50MHz, 48-lead LVDS218
Untitled Abstract: No abstract text available Text: Standard Products LVDS218 Deserializer Data Sheet December, 2008 FEATURES INTRODUCTION The LVDS218 Deserializer converts the three LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 75MHz, 21 bits of TTL data are transmitted at a	Original	PDF	UT54LVDS218 75MHz MIL-STD-883 48-lead
5962 38535 Abstract: No abstract text available Text: Standard Products LVDS218 Deserializer Data Sheet May 24, 2002 FEATURES INTRODUCTION q q q q q 15 to 50MHz shift clock support 50% duty cycle on receiver output clock Low power consumption Cold sparing all pins Power-down mode <200µW max The LVDS218 Deserializer converts the three LVDS data	Original	PDF	UT54LVDS218 50MHz 50MHz, 48-lead 5962 38535
US transmitter receiver Abstract: 54LVDS218 UT54LVDS218 LVDS217 LVDS218 Text: Standard Products LVDS218 Deserializer Data Sheet October 2002 FEATURES INTRODUCTION q q q q q q q q q q q q The LVDS218 Deserializer converts the three LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 50MHz, 21 bits of TTL data are transmitted at a	Original	PDF	UT54LVDS218 50MHz, 50MHz 48-lead US transmitter receiver 54LVDS218 LVDS217 LVDS218
54LVDS218 Abstract: UT54LVDS218 LVDS217 marking RAD Text: Standard Products LVDS218 Deserializer Data Sheet April, 2002 FEATURES INTRODUCTION q q q q q 15 to 75 MHz shift clock support 50% duty cycle on receiver output clock Low power consumption Cold sparing all pins Power-down mode <200µW max The LVDS218 Deserializer converts the three LVDS data	Original	PDF	UT54LVDS218 48-lead 54LVDS218 LVDS217 marking RAD
mark 3t1 Abstract: lvds228 PT-EP2C70-1 Cyclone II EP2C70 Text: Cyclone II EP2C70 Device Pin-Out PT-EP2C70-1.7 2008 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or	Original	PDF	EP2C70 PT-EP2C70-1 mark 3t1 lvds228 Cyclone II EP2C70
Untitled Abstract: No abstract text available Text: Standard Products LVDS218 Deserializer Advanced Data Sheet October 24, 2001 FEATURES INTRODUCTION q q q q q 15 to 75 MHz shift clock support 50% duty cycle on receiver output clock Low power consumption Cold sparing all pins Power-down mode <200µW max	Original	PDF	UT54LVDS218 48-lead
Untitled Abstract: No abstract text available Text: Standard Products LVDS218 Deserializer Advanced Data Sheet May 7, 2001 FEATURES INTRODUCTION q q q q q q q q q q q q q The LVDS218 Deserializer converts the three LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 75 MHz, 21 bits of TTL data are transmitted at a	Original	PDF	UT54LVDS218 MIL-STD-883
54LVDS218 Abstract: LVDS217 Text: Standard Products LVDS218 Deserializer Advanced Data Sheet February, 2002 FEATURES INTRODUCTION q q q q q 15 to 75 MHz shift clock support 50% duty cycle on receiver output clock Low power consumption Cold sparing all pins Power-down mode <200µW max	Original	PDF	UT54LVDS218 48-lead 54LVDS218 LVDS217

54LVDS218 Abstract: UT54LVDS218 lvds217 Aeroflex UTMC lvds receiver LVDS218 Text: Standard Products LVDS218 Deserializer Data Sheet December, 2008 FEATURES INTRODUCTION The LVDS218 Deserializer converts the three LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 75MHz, 21 bits of TTL data are transmitted at a	Original	PDF	UT54LVDS218 75MHz, 525Mbps 75MHz 54LVDS218 lvds217 Aeroflex UTMC lvds receiver LVDS218
Untitled Abstract: No abstract text available Text: Standard Products LVDS218 Deserializer Advanced Data Sheet October 4, 2001 FEATURES INTRODUCTION q q q q q 15 to 75 MHz shift clock support 50% duty cycle on receiver output clock Low power consumption Cold sparing all pins Power-down mode <200µW max	Original	PDF	UT54LVDS218 48-lead
Aeroflex UTMC lvds receiver Abstract: No abstract text available Text: Standard Products LVDS218 Deserializer Data Sheet September 24, 2003 INTRODUCTION FEATURES The LVDS218 Deserializer converts the three LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 75MHz, 21 bits of TTL data are transmitted at a	Original	PDF	UT54LVDS218 75MHz MIL-STD-883 48-lead Aeroflex UTMC lvds receiver