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    LVCH16373A Search Results

    LVCH16373A Result Highlights (5)

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    74LVCH16373APAG8 Renesas Electronics Corporation 3.3V CMOS 16-Bit Transparent D-Type Latch with 3-State Outputs, 5.0V Tolerant I/O, and Bus-Hold Visit Renesas Electronics Corporation
    74LVCH16373APAG Renesas Electronics Corporation 3.3V CMOS 16-Bit Transparent D-Type Latch with 3-State Outputs, 5.0V Tolerant I/O, and Bus-Hold Visit Renesas Electronics Corporation
    74LVCH16373ADGGRG4 Texas Instruments 16-Bit Transparent D-Type Latch With 3-State Outputs 48-TSSOP -40 to 125 Visit Texas Instruments Buy
    SN74LVCH16373ADLR Texas Instruments 16-Bit Transparent D-Type Latch With 3-State Outputs 48-SSOP -40 to 125 Visit Texas Instruments Buy
    SN74LVCH16373ADL Texas Instruments 16-Bit Transparent D-Type Latch With 3-State Outputs 48-SSOP -40 to 125 Visit Texas Instruments Buy
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    LVCH16373A Price and Stock

    Texas Instruments SN74LVCH16373ADGGR

    IC TRANSP LATCH TRI-ST 48-TSSOP
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    DigiKey SN74LVCH16373ADGGR Cut Tape 3,413 1
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    Nexperia 74LVCH16373ADGV-QJ

    74LVCH16373ADGV-Q100/SOT480/TS
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    Texas Instruments SN74LVCH16373ADLR

    IC TRANSP LATCH TRI-ST 48-SSOP
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    Texas Instruments SN74LVCH16373ADGVR

    IC TRANSP LATCH TRI-ST 48-TVSOP
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    Texas Instruments SN74LVCH16373ADL

    IC TRANSP LATCH TRI-ST 48-SSOP
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    Find more LVCH16373A price and stock on Findchips.com

    LVCH16373A Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    IDT74LVCH16373A

    Abstract: LVCH16373A
    Text: LVCH16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT LVCH16373A TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD DESCRIPTION FEATURES: The LVCH16373A 16-bit transparent D-type latch is built using advanced


    Original     		IDT74LVCH16373A 16-BIT 16-BIT LVCH16373A IDT74LVCH16373A PDF

    Untitled

    Abstract: No abstract text available
    Text: LVCH16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT LVCH16373A TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD DESCRIPTION FEATURES: The LVCH16373A 16-bit transparent D-type latch is built using advanced


    Original     		IDT74LVCH16373A 16-BIT 16-BIT LVCH16373A PDF

    74LVC16373A

    Abstract: 74LVC16373ADGG 74LVC16373ADL 74LVCH16373A 74LVCH16373ADGG 74LVCH16373ADL TSSOP48
    Text: INTEGRATED CIRCUITS DATA SHEET 74LVC16373A; LVCH16373A 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state Product specification Supersedes data of 2002 Oct 02 2003 Dec 08 Philips Semiconductors Product specification 16-bit D-type transparent latch with 5 V


    Original     		74LVC16373A; 74LVCH16373A 16-bit 74LVC 6373A SCA75 74LVC16373A 74LVC16373ADGG 74LVC16373ADL 74LVCH16373A 74LVCH16373ADGG 74LVCH16373ADL TSSOP48 PDF

    IDT74LVCH16373A

    Abstract: LVCH16373A
    Text: Integrated Device Technology, Inc. 3.3V CMOS 16-BIT TRANSPARENT LATCH WITH BUS HOLD AND 5 VOLT TOLERANT I/O LVCH16373A ADVANCE INFORMATION FEATURES: DESCRIPTION: • Common features: – Typical tSK o (Output Skew) < 250ps – ESD > 2000V per MIL-STD-883, Method 3015;


    Original     		16-BIT IDT74LVCH16373A 250ps MIL-STD-883, 200pF, LVCH16373A: 16-BIT O48-1) O48-3) IDT74LVCH16373A LVCH16373A PDF

    A115-A

    Abstract: SN74LVCH16373A SN74LVCH16373ADL SN74LVCH16373AGRDR SN74LVCH16373AZRDR
    Text: LVCH16373A 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCAS568M – MARCH 1996 – REVISED FEBRUARY 2006 FEATURES • • • • • • • • DGG, DGV, OR DL PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Typical VOLP (Output Ground Bounce)


    Original     		SN74LVCH16373A 16-BIT SCAS568M 000-V A114-A) A115-A SN74LVCH16373A SN74LVCH16373ADL SN74LVCH16373AGRDR SN74LVCH16373AZRDR PDF

    74LVC05

    Abstract: 7400 datasheet 2-input nand gate 74LVC05A LVC1G04 transistor x1 pv 25 inverter board design pv 74ALVC1G04 74ALVCH244 7400 nand gate series 74ALVC1G14
    Text: Selector Guide for ALVC/LVC Products the leading provider of high-performance logic. From single-gate to 32-bit, IDT is your source for ALVC/LVC logic. Today’s designers are developing the most challenging telecommunications, networking and PC products ever designed


    Original     		32-bit, compatibilit-7850 74LVC05 7400 datasheet 2-input nand gate 74LVC05A LVC1G04 transistor x1 pv 25 inverter board design pv 74ALVC1G04 74ALVCH244 7400 nand gate series 74ALVC1G14 PDF

    Untitled

    Abstract: No abstract text available
    Text: LVCH16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT LVCH16373A TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD FEATURES: DESCRIPTION • Typical tSK o (Output Skew) < 250ps


    Original     		IDT74LVCH16373A 16-BIT 250ps MIL-STD-883, 200pF, LVCH16373A PDF

    Untitled

    Abstract: No abstract text available
    Text: LVCH16373A 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCAS568M – MARCH 1996 – REVISED FEBRUARY 2006 FEATURES • • • • • • • • DGG, DGV, OR DL PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Typical VOLP (Output Ground Bounce)


    Original     		SN74LVCH16373A 16-BIT SCAS568M 000-V A114-A) A115-A) PDF

    smd 1le

    Abstract: No abstract text available
    Text: INTEGRATED CIRCUITS DATA SHEET 74LVC16373A; LVCH16373A 16-bit D-type transparent latch with 5 V tolerant inputs/outputs 3-state Product specification Supersedes data of 1998 Mar 17 2002 Sep 12 Philips Semiconductors Product specification 16-bit D-type transparent latch with 5 V


    Original     		74LVC16373A; 74LVCH16373A 16-bit smd 1le PDF

    Untitled

    Abstract: No abstract text available
    Text: LVCH16373A 16ĆBIT TRANSPARENT DĆTYPE LATCH WITH 3ĆSTATE OUTPUTS SCAS568L − MARCH 1996 − REVISED SEPTEMBER 2003 D Member of the Texas Instruments D D D D D D D DGG, DGV, OR DL PACKAGE TOP VIEW Widebus  Family Typical VOLP (Output Ground Bounce)


    Original     		SN74LVCH16373A 16BIT SCAS568L 000-V A114-A) A115-A) PDF

    Untitled

    Abstract: No abstract text available
    Text: LVCH16373A 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SCAS568H – MARCH 1996 – REVISED OCTOBER 2000 D D D D D D D D Member of Texas Instruments’ Widebus  Family Typical VOLP Output Ground Bounce <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		SN74LVCH16373A 16-BIT SCAS568H 000-V A114-A) A115-A) SN74LVCH16373ADGGR SN74LVCH16373ADGVR SN74LVCH16373ADL PDF

    LVCH16373

    Abstract: A115-A SN74LVCH16373A SN74LVCH16373ADGGR SN74LVCH16373ADL SN74LVCH16373ADLR LVCH1637
    Text: LVCH16373A 16ĆBIT TRANSPARENT DĆTYPE LATCH WITH 3ĆSTATE OUTPUTS SCAS568L − MARCH 1996 − REVISED SEPTEMBER 2003 D Member of the Texas Instruments D D D D D D D DGG, DGV, OR DL PACKAGE TOP VIEW Widebus  Family Typical VOLP (Output Ground Bounce)


    Original     		SN74LVCH16373A 16BIT SCAS568L 000-V A114-A) A115-A) LVCH16373 A115-A SN74LVCH16373A SN74LVCH16373ADGGR SN74LVCH16373ADL SN74LVCH16373ADLR LVCH1637 PDF

    Untitled

    Abstract: No abstract text available
    Text: LVCH16373A 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCAS568M – MARCH 1996 – REVISED FEBRUARY 2006 FEATURES • • • • • • • • DGG, DGV, OR DL PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Typical VOLP (Output Ground Bounce)


    Original     		SN74LVCH16373A 16-BIT SCAS568M 000-V PDF

    IDT74LVCH16373A

    Abstract: LVCH16373A
    Text: LVCH16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT LVCH16373A TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD FEATURES: DESCRIPTION • Typical tSK o (Output Skew) < 250ps


    Original     		IDT74LVCH16373A 16-BIT 16-BIT 250ps MIL-STD-883, 200pF, LVCH16373A IDT74LVCH16373A PDF

    Untitled

    Abstract: No abstract text available
    Text: LVCH16373A 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCAS756 – DECEMBER 2003 – REVISED DECEMBER 2005 FEATURES • • • • • • • • DGG, DGV, OR DL PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family


    Original     		SN74LVCH16373A 16-BIT SCAS756 000-V A114-A) A115-A) PDF

    A115-A

    Abstract: SN74LVCH16373A SN74LVCH16373ADL SN74LVCH16373AGRDR SN74LVCH16373AZRDR
    Text: LVCH16373A 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCAS568M – MARCH 1996 – REVISED FEBRUARY 2006 FEATURES • • • • • • • • DGG, DGV, OR DL PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Typical VOLP (Output Ground Bounce)


    Original     		SN74LVCH16373A 16-BIT SCAS568M 000-V A114-A) A115-A SN74LVCH16373A SN74LVCH16373ADL SN74LVCH16373AGRDR SN74LVCH16373AZRDR PDF

    A115-A

    Abstract: SN74LVCH16373A SN74LVCH16373ADL SN74LVCH16373ADLR
    Text: LVCH16373A 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SCAS568K – MARCH 1996 – REVISED MARCH 2002 D D D D D D D D DGG, DGV, OR DL PACKAGE TOP VIEW Member of the Texas Instruments Widebus  Family Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C


    Original     		SN74LVCH16373A 16-BIT SCAS568K 000-V A114-A) A115-A) A115-A SN74LVCH16373A SN74LVCH16373ADL SN74LVCH16373ADLR PDF

    LVC16245

    Abstract: philips semiconductor data handbook LCX16245 lcx245 SN74ALVCH16245 SN74LV245 SCAA001 SN74LVC245 SN74LVC245A SN74LVCH245
    Text: LVC CHARACTERIZATION INFORMATION 1 LVC COMPARISON TO OTHER LOWĆVOLTAGE LOGIC FAMILIES 2 LVC AND 5ĆV TOLERANCE A 5ĆV TOLERANT LVC - RELEASED DEVICES B FREQUENTLY ASKED QUESTIONS C TI'S LOWĆVOLTAGE PORTFOLIO D ADVANCED PACKAGING E LVC DESIGNER'S GUIDE SCBA010


    Original     		SCBA010 SN74LVC16245A SSYU001B. LVC16245 philips semiconductor data handbook LCX16245 lcx245 SN74ALVCH16245 SN74LV245 SCAA001 SN74LVC245 SN74LVC245A SN74LVCH245 PDF

    A115-A

    Abstract: SN74LVCH16373A SN74LVCH16373ADL SN74LVCH16373ADLR
    Text: LVCH16373A 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SCAS568I – MARCH 1996 – REVISED MARCH 2001 D D D D D D D D DGG, DGV, OR DL PACKAGE TOP VIEW Member of Texas Instruments’ Widebus Family Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C


    Original     		SN74LVCH16373A 16-BIT SCAS568I 000-V A114-A) A115-A) A115-A SN74LVCH16373A SN74LVCH16373ADL SN74LVCH16373ADLR PDF

    lvch16373a

    Abstract: No abstract text available
    Text: LVCH16373A 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SCAS568J – MARCH 1996 – REVISED SEPTEMBER 2001 D D D D D D D D DGG, DGV, OR DL PACKAGE TOP VIEW Member of the Texas Instruments Widebus  Family Typical VOLP (Output Ground Bounce)


    Original     		SN74LVCH16373A 16-BIT SCAS568J 000-V A114-A) A115-A) 16-bit lvch16373a PDF

    Untitled

    Abstract: No abstract text available
    Text: LVCH16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD DESCRIPTION: FEATURES: - The LVCH16373A 16-bit transparent D-type latch is built using advanced dual metal CMOS technology. This high­ speed, low-power latch is ideal for tem porary storage of


    OCR Scan     		IDT74LVCH16373A 16-BIT LVCH16373A 16-bit PDF

    Untitled

    Abstract: No abstract text available
    Text: Integra ted D evice Technology, inc. 3.3V C M O S 16-BIT T R A N S P A R E N T LATCH WITH BUS HO LD AND 5 VOLT T O L E R A N T I/O IDT74LVCH1 6373A ADVANCE INFORMATION FE ATURES: DESCRIPTION: • C o m m o n feat ures: The LVCH16373A16-bit transparent D-type latches are built


    OCR Scan     		16-BIT IDT74LVCH1 250ps MIL-STD-883, 200pF, PDF

    lvch16373a

    Abstract: No abstract text available
    Text: LVCH16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD DESCRIPTION: FEATURES: - The LVCH16373A 16-bit transparent D-type latch is built using advanced dual metal CMOS technology. This high­ speed, low-power latch is ideal for tem porary storage of


    OCR Scan     		IDT74LVCH16373A 16-BIT 250ps MIL-STD-883, 200pF, 635mm LVCH16373A PDF

    Untitled

    Abstract: No abstract text available
    Text: 3.3V CMOS 16-BIT LVCH16373A TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD FEATURES: - Typical tsK o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) 0.635mm pitch SSOP, 0.50mm pitch TSSOP


    OCR Scan     		16-BIT IDT74LVCH16373A 250ps MIL-STD-883, 200pF, 635mm LVCH16373A LVCH16373A 16-bit 48-Pin PDF