lpec

Contextual Info: RECTIFIERS SES5801 SES5802 SES5803 High Efficiency, 60A FEATURES • Low Forward Voltage • Fast Switching Speeds • High Surge Capability • Low Thermal Resistance • Mechanically Rugged DO-5 Package • Reverse Polarity Available DESCRIPTION The SES, super-fast recovery, rectifiers are

ultrasparc

Contextual Info: UltraSPARC “-!! Data Buffer UDB-II DATA SHEET Companion Device for 250/300 MHz UltraSPARC-II Systems D e s c r ip t io n The UltraSPARC-II Data Buffer (UDB-II) consists of two identical ASICs connecting the UltraSPARC-II micro­ processor and its E-Cache to the system data bus (i.e., UPA bus). These two are designated UDB_H (for the

EDS1616AGTA

Abstract: EDS1616AGTA-6B-E EDS1616AGTA-75-E
Contextual Info: DATA SHEET 16M bits SDRAM EDS1616AGTA 1M words x 16 bits Description Pin Configurations The EDS1616AGTA is 16M bits SDRAM organized as 524,288 words × 16 bits × 2 banks. All inputs and outputs are synchronized with the positive edge of the clock. It is packaged in 50-pin plastic TSOP (II).

Contextual Info: PC/100 SDRAM HM5216805-A60, HM5216405-A60 1,048,576-word x 8-bit x 2-bank Synchronous Dynamic RAM 2,097,152-word x 4-bit x 2-bank Synchronous Dynamic RAM HITACHI ADE-203-796 Z Preliminary Rev. 0.1 Sep. 19, 1997 Description All inputs and outputs are referred to the rising edge of the clock input. The HM 5216805 Series,

HM5264165-B60

Abstract: HM5264805-B60 sdram 4 bank 4096 16 HM5264165 HM5264165TT-B60 Hitachi DSA00196
Contextual Info: HM5264165-B60 HM5264805-B60 HM5264405-B60 64M LVTTL interface SDRAM 100 MHz 1-Mword x 16-bit × 4-bank/2-Mword × 8-bit × 4-bank /4-Mword × 4-bit × 4-bank PC/100 SDRAM ADE-203-832C Z Rev. 1.0 Jun. 25, 1998 Description The Hitachi HM5264165 is a 64-Mbit SDRAM organized as 1048576-word × 16-bit × 4 bank. The Hitachi

143-PIN

Contextual Info: DATA SHEET 256MB SDRAM Micro DIMM EBS25UC8APMA 32M words x 64 bits, 1 bank Description Features The EBS25UC8APMA is 32M words × 64 bits, 1 bank Synchronous Dynamic RAM Micro Dual In-line Memory Module (Micro DIMM), mounted 8 pieces of 256M bits SDRAM sealed in µBGA package. This module

HM5264805LTT-B60

Abstract: HM5264805LTTB60 HM5264805TT-B60 Hitachi DSA00164
Contextual Info: HM5264165-B60 HM5264805-B60 HM5264405-B60 64M LVTTL interface SDRAM 100 MHz 1-Mword x 16-bit × 4-bank/2-Mword × 8-bit × 4-bank /4-Mword × 4-bit × 4-bank PC/100 SDRAM ADE-203-832D Z Rev. 2.0 Oct. 20, 1998 Description The Hitachi HM5264165 is a 64-Mbit SDRAM organized as 1048576-word × 16-bit × 4 bank. The Hitachi

EDS2504ACTA

Abstract: EDS2504APTA EDS2508ACTA EDS2508APTA EDS2516ACTA EDS2516APTA
Contextual Info: DATA SHEET 256M bits SDRAM EDS2504ACTA, EDS2504APTA 64M words x 4 bits EDS2508ACTA, EDS2508APTA (32M words × 8 bits) EDS2516ACTA, EDS2516APTA (16M words × 16 bits) Description Pin Configurations The EDS2504AC/AP is a 256M bits SDRAM organized as 16,777,216 words × 4 bits × 4 banks. The EDS2508

Hitachi DSA00164

Contextual Info: HM5251165B-75/A6/B6 HM5251805B-75/A6/B6 HM5251405B-75/A6/B6 512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword x 16-bit × 4-bank/16-Mword × 8-bit × 4-bank /32-Mword × 4-bit × 4-bank PC/133, PC/100 SDRAM ADE-203-1095 Z Preliminary Rev. 0.0 Sep. 1, 1999

Hitachi DSA00171

Contextual Info: HM5212165 シリ−ズ HM5212805 シリ−ズ 128M LVTTL interface SDRAM 66 MHz 2-Mword x 16-bit × 4-bank/4-Mword × 8-bit × 4-bank ADJ-203-289A Z ’98. 7.1 Rev. 1.0 概要 HM5212165 シリーズは，2097152 ワード × 16 ビット × 4 バンク構成の SDRAM です。HM5212805 シリー

Hitachi DSA00167

Contextual Info: HB52D88GB-F 64 MB Unbuffered SDRAM Micro DIMM 8-Mword x 64-bit, 100 MHz Memory Bus, 1-Bank Module 4 pcs of 8 M × 16 components PC100 SDRAM ADJ-203-519 (Z) ’00 . 1. 13 暫定仕様 Rev. 0.0 概要 HB52D88GB は， 128M ビット SDRAM HM5212165FTD （TSOP パッケージ）

5264805

Abstract: HM5264805 Series Hitachi DSA00164
Contextual Info: HM5264165 Series HM5264805 Series HM5264405 Series 64M LVTTL interface SDRAM 125 MHz/100 MHz 1-Mword x 16-bit × 4-bank/2-Mword × 8-bit × 4-bank/ 4-Mword × 4-bit × 4-bank ADE-203-497C Z Rev. 1.0 July 1, 1998 Description The Hitachi HM5264165 is a 64-Mbit SDRAM organized as 1048576-word × 16-bit × 4 bank. The Hitachi

EDS2532AABJ-6B

Contextual Info: DATA SHEET 256M bits SDRAM EDS2532AABJ-6B 8M words x 32 bits Description Pin Configurations The EDS2532AABJ is a 256M bits SDRAM organized as 2,097,152 words × 32 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the clock.

EDS1216AATA-75E

Abstract: EDS1216AATA EDS1216AATA-75-E
Contextual Info: DATA SHEET 128M bits SDRAM EDS1216AATA 8M words x 16 bits Description Pin Configurations The EDS1216AATA is a 128M bits SDRAM organized as 2,097,152 words × 16 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the clock.

Contextual Info: DATA SHEET 256MB Unbuffered SDRAM DIMM EBS25UC8APFA 32M words x 64 bits, 1 bank Description Features The EBS25UC8APFA is 32M words × 64 bits, 1 bank Synchronous Dynamic RAM Unbuffered Module, mounted 8 pieces of 256M bits SDRAM sealed in TSOP package. This module provides high density

Contextual Info: PRELIMINARY DATA SHEET 256MB Unbuffered SDRAM Micro DIMM HB52RF328GB-B 32M words x 64 bits, 1 bank HB52RD328GB-B (32M words × 64 bits, 1 bank) Features Description EO L The HB52RF328GB and HB52RD328GB are a 32M × 64 × 1 banks Synchronous Dynamic RAM Micro Dual

Contextual Info: DATA SHEET 256MB Unbuffered SDRAM DIMM EBS25EC8APFA 32M words x 72 bits, 1 bank Description Features The EBS25EC8APFA is 32M words × 72 bits, 1 bank Synchronous Dynamic RAM Unbuffered Module, mounted 9 pieces of 256M bits SDRAM sealed in TSOP package. This module provides high density

EBS25EC8APFA

Abstract: EBS25EC8APFA-75 EBS25EC8APFA-7A EDS2508APTA
Contextual Info: DATA SHEET 256MB Unbuffered SDRAM DIMM EBS25EC8APFA 32M words x 72 bits, 1 bank Description Features The EBS25EC8APFA is 32M words × 72 bits, 1 bank Synchronous Dynamic RAM Unbuffered Module, mounted 9 pieces of 256M bits SDRAM sealed in TSOP package. This module provides high density

EDS6416AHBH

Abstract: EDS6416AHBH-6B-E EDS6416CHBH
Contextual Info: DATA SHEET 64M bits SDRAM EDS6416AHBH, EDS6416CHBH 4M words x 16 bits Description Pin Configurations The EDS6416AHBH, EDS6416CHBH are 64M bits SDRAMs organized as 1,048,576 words × 16 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the clock.

EDS2532JEBH-75

Contextual Info: PRELIMINARY DATA SHEET 256M bits SDRAM EDS2532JEBH-75 8M words x 32 bits Description Pin Configurations The EDS2532JEBH is a 256M bits SDRAM organized as 2,097,152 words × 32 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the

EDS2532EEBH-9A

Contextual Info: PRELIMINARY DATA SHEET 256M bits SDRAM EDS2532EEBH-9A 8M words x 32 bits Description Pin Configurations The EDS2532EEBH is a 256M bits SDRAM organized as 2,097,152 words × 32 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the

EDS6416AHTA

Abstract: EDS6416AHTA-75TI-E EDS6416AHTA-TI
Contextual Info: PRELIMINARY DATA SHEET 64M bits SDRAM WTR Wide Temperature Range EDS6416AHTA-TI (4M words x 16 bits) Description Pin Configurations The EDS6416AHTA is a 64M bits SDRAMs organized as 1,048,576 words × 16 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the

EDS2516ADTA-75

Contextual Info: PRELIMINARY DATA SHEET 256M bits SDRAM EDS2516ADTA-75 16M words x 16 bits Description Pin Configurations The EDS2516ADTA is 256M bits SDRAMs organized as 4,194,304 words × 16 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the

EDS2732CABH

Contextual Info: DATA SHEET 256M bits SDRAM EDS2732CABH 8M words x 32 bits Description Pin Configurations The EDS2732CA is a 256M bits SDRAM organized as 2,097,152 words × 32 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the clock.