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    LOGIC GATES CIRCUIT DIAGRAM Search Results

    LOGIC GATES CIRCUIT DIAGRAM Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    74HC4053FT Toshiba Electronic Devices & Storage Corporation CMOS Logic IC, SPDT(1:2)/Analog Multiplexer, TSSOP16B, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation
    74HC4051FT Toshiba Electronic Devices & Storage Corporation CMOS Logic IC, SP8T(1:8)/Analog Multiplexer, TSSOP16B, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation
    TB67H481FTG Toshiba Electronic Devices & Storage Corporation Stepping and Brushed Motor Driver /Bipolar Type / Vout(V)=50 / Iout(A)=3.0 / IN input type / VQFN32 Visit Toshiba Electronic Devices & Storage Corporation
    TLP2701 Toshiba Electronic Devices & Storage Corporation Photocoupler (photo-IC output), 5000 Vrms, 4pin SO6L Visit Toshiba Electronic Devices & Storage Corporation
    TCKE800NA Toshiba Electronic Devices & Storage Corporation eFuse IC (electronic Fuse), 4.4 to 18 V, 5.0 A, Auto-retry, WSON10B Visit Toshiba Electronic Devices & Storage Corporation

    LOGIC GATES CIRCUIT DIAGRAM Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    spckt_10003.0

    Abstract: No abstract text available
    Text: Category: Special Circuits CIRCUIT IDEAS FOR DESIGNERS Schematic no. SPCKT_10003.0 0.2V Supply Voltage Nanopower Two-Input NOR and NAND gates Description Simple logic gates such as NOR and NAND gates can be readily implemented using EPAD MOSFETs to operate


    Original     		200mV ALD110802) spckt_10003.0 PDF

    TC4081BP

    Abstract: DIP14-P-300-2 TC4081B TC4081BF TC4081BFN
    Text: TC4081BP/BF/BFN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC4081BP,TC4081BF,TC4081BFN TC4081B Quad 2-Input AND Gate TC4081B is positive logic AND gates with two inputs respectively. Since all the outputs of these gates are equipped with the


    Original     		TC4081BP/BF/BFN TC4081BP TC4081BF TC4081BFN TC4081B TC4081BP TC4081BF TC4081B DIP14-P-300-2 TC4081BFN PDF

    tc4081bp

    Abstract: No abstract text available
    Text: TC4081BP/BF/BFN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC4081BP,TC4081BF,TC4081BFN TC4081B Quad 2-Input AND Gate TC4081B is positive logic AND gates with two inputs respectively. Since all the outputs of these gates are equipped with the


    Original     		TC4081BP/BF/BFN TC4081BP TC4081BF TC4081BFN TC4081B TC4081BP TC4081BF TC4081B PDF

    TC4081BP

    Abstract: No abstract text available
    Text: TC4081BP/BF/BFN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC4081BP,TC4081BF,TC4081BFN TC4081B Quad 2-Input AND Gate TC4081B is positive logic AND gates with two inputs respectively. Since all the outputs of these gates are equipped with the


    Original     		TC4081BP/BF/BFN TC4081BP TC4081BF TC4081BFN TC4081B TC4081BP TC4081BF TC4081B PDF

    TC4081BP

    Abstract: DIP14-P-300-2 TC4081B TC4081BF TC4081BFN
    Text: TC4081BP/BF/BFN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC4081BP,TC4081BF,TC4081BFN TC4081B Quad 2-Input AND Gate TC4081B is positive logic AND gates with two inputs respectively. Since all the outputs of these gates are equipped with the


    Original     		TC4081BP/BF/BFN TC4081BP TC4081BF TC4081BFN TC4081B TC4081BP TC4081BF TC4081B DIP14-P-300-2 TC4081BFN PDF

    Untitled

    Abstract: No abstract text available
    Text: TC4081BP/BF/BFN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC4081BP,TC4081BF,TC4081BFN TC4081B Quad 2-Input AND Gate TC4081B is positive logic AND gates with two inputs respectively. Since all the outputs of these gates are equipped with the


    Original     		TC4081BP/BF/BFN TC4081BP TC4081BF TC4081BFN TC4081B TC4081BP TC4081BF TC4081B PDF

    Untitled

    Abstract: No abstract text available
    Text: TC4071BFN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC4071BFN TC4071B Quad 2-Input OR Gate TC4071B is positive logic OR gates with two inputs respectively. As all the outputs of gates are equipped with the buffer circuits of inverters, the input/output propagation


    Original     		TC4071BFN TC4071B SOL14-P-150-1 TC4071B PDF

    DM7400

    Abstract: DM7400M DM7400N M14A MS-001 N14A
    Text: Revised July 2001 DM7400 Quad 2-Input NAND Gates General Description This device contains four independent gates each of which performs the logic NAND function. Ordering Code: Order Number Package Number DM7400M M14A 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, 0.150" Narrow


    Original     		DM7400 DM7400M 14-Lead MS-012, DM7400N MS-001, DM7400 DM7400M DM7400N M14A MS-001 N14A PDF

    Untitled

    Abstract: No abstract text available
    Text: TC4081BFN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC4081BFN TC4081B Quad 2-Input AND Gate TC4081B is positive logic AND gates with two inputs respectively. Since all the outputs of these gates are equipped with the buffer circuits of inverters, the input/output propagation


    Original     		TC4081BFN TC4081B SOL14-P-150-1 TC4081B PDF

    DM74LS04

    Abstract: DM74LS04 HEX INVERTING GATES DM74LS04N DM74LS04M DM74LS04SJ M14A M14D MS-001 N14A
    Text: Revised March 2000 DM74LS04 Hex Inverting Gates General Description This device contains six independent gates each of which performs the logic INVERT function. Ordering Code: Order Number Package Number Package Description DM74LS04M M14A 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-120, 0.150 Narrow


    Original     		DM74LS04 DM74LS04M 14-Lead MS-120, DM74LS04SJ DM74LS04N MS-001, DM74LS04 DM74LS04 HEX INVERTING GATES DM74LS04N DM74LS04M DM74LS04SJ M14A M14D MS-001 N14A PDF

    Untitled

    Abstract: No abstract text available
    Text: TC4071BP/BF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC4071BP,TC4071BF TC4071B Quad 2-Input OR Gate TC4071B is positive logic OR gates with two inputs respectively. As all the outputs of gates are equipped with the buffer circuits of inverters, the input/output propagation


    Original     		TC4071BP/BF TC4071BP TC4071BF TC4071B TC4071BP DIP14-P-300-2 OP14-P-300-1 TC4071B PDF

    74AS1804

    Abstract: No abstract text available
    Text: MITSUBISHI ASTTLs -*00°° M 74AS1804P HEX 2-INPUT NAND DRIVER DESCRIPTION The M74AS1804P is a semiconductor integrated circuit consisting of six 2-input positive-logic NAND buffer gates, usable as negative-logic NOR buffer gates. PIN CONFIGURATION TOP VIEW


    OCR Scan     		74AS1804P M74AS1804P 74AS1804 PDF

    M74AS02P

    Abstract: No abstract text available
    Text: MITSUBISHI ASTTLs M74AS02P ŸŸ& 0 QUADRUPLE 2-INPUT POSITIVE NOR GATE DESCRIPTION PIN CONFIGURATION TOP VIEW The M74AS02P is a semiconductor integrated circuit consisting of four 2-input positive-logic NOR gates, us­ able as negative-logic NAND gates.


    OCR Scan     		M74AS02P M74AS02P PDF

    74LS132P

    Abstract: M74LS14P
    Text: MITSUBISHI LSTTLs M74LS132P QUADRUPLE 2-IN P U T PO SITIVE NAND SCHM ITT TRIGGER DESCRIPTION The M74LS132P is a semiconductor integrated circuit containing four 2-input positive-logic NAND gates having a Schmitt trigger function and negative-logic NOR gates.


    OCR Scan     		M74LS132P M74LS132P 500ns, b2LHfl27 0013Sbl 14-PIN 16-PIN 20-PIN 74LS132P M74LS14P PDF

    74AS1000

    Abstract: No abstract text available
    Text: MITSUBISHI A STTLs M 74AS1000AP QUADRUPLE 2-INPUT POSITIVE NAND DRIVER DESCRIPTION PIN CONFIGURATION TOP VIEW The M74AS1000AP is a semiconductor integrated circuit consisting of four 2-input positive-logic NAND buffer gates, usable as negative-logic NOR buffer gates.


    OCR Scan     		74AS1000AP M74AS1000AP -----h75 74AS1000 PDF

    Untitled

    Abstract: No abstract text available
    Text: MITSUBISHI ASTTLs M74AS08P QUADRUPLE 2-INPUT POSITIVE AND GATE DESCRIPTION PIN CONFIGURATION TOP VIEW The M74AS08P is a semiconductor integrated circuit consisting of four 2-input positive-logic AND gates, us­ able as negative-logic OR gates. FEATURES • High speed


    OCR Scan     		M74AS08P M74AS08P PDF

    74LS00P

    Abstract: M74LS00P
    Text: M IT S U B IS H I LSTTLs M74LS00P QUADRUPLE 2-IN P U T POSITIVE NAND GATES DESCRIPTION The M 74LS 00P is semiconductor integrated circuit contain­ ing fo u r dual-input positive-logic N A N D gates, usable as negative-logic N O R gates. FEATURES • High breakdown input voltage V | S 15 V


    OCR Scan     		M74LS00P 0013Sbl 14-PIN 16-PIN 20-PIN 74LS00P M74LS00P PDF

    M74LS00P

    Abstract: 20-PIN M74LS00
    Text: M IT S U B IS H I LSTTLs M74LS00P QUADRUPLE 2-IN P U T POSITIVE NAND GATES DESCRIPTION The M 74LS 00P is semiconductor integrated circuit contain­ ing fo u r dual-input positive-logic N A N D gates, usable as negative-logic N O R gates. FEATURES • High breakdown input voltage V | S 15 V


    OCR Scan     		M74LS00P M74LS00P 16-PIN 20-PIN M74LS00 PDF

    IC TTL 74LS00

    Abstract: 74ls00 74LS00 gate diagram
    Text: MITSUBISHI HIGH SPEED CMOS M74HCT00P/FP/DP QUADRUPLE 2-INPUT POSITIVE NAND GATE WITH L S TTL-C O M P A TIB LE INPUTS DESCRIPTION The M74HCT00P is a semiconductor integrated circuit con­ sisting of four 2-input positive-logic NAND gates, usable as negative-logic NOR gates.


    OCR Scan     		M74HCT00P/FP/DP M74HCT00P 74LSTTL G--06 IC TTL 74LS00 74ls00 74LS00 gate diagram PDF

    74ls20 mitsubishi

    Abstract: No abstract text available
    Text: MITSUBISHI HIGH S P E E D CMOS M74HC20P/FP/DP DUAL 4-INPUT P O S IT IV E NAND GATE DESCRIPTION The M74HC20 is a semiconductor integrated circuit con­ sisting of two 4-input positive-logic NAND gates, usable as negative-logic NOR gates. PIN CONFIGURATION TOP VIEW


    OCR Scan     		M74HC20P/FP/DP M74HC20 74LSTTL 14P2P 14-PIN 16P2P 16-PIN 20P2V 20-PIN 74ls20 mitsubishi PDF

    74LS18P

    Abstract: No abstract text available
    Text: MITSUBISHI LSTTLs M 74LS 18P DUAL 4-IN P U T NAND SCHMITT TRIGGER DESCRIPTION The M 74LS 18P is a semiconductor integrated circuit PIN CONFIGURATION TOP VIEW containing tw o 4-input positive-logic N A N D gates having a schm itt trigger function and negative-logic N O R gates.


    OCR Scan     		500ns, b2LHfl27 0013Sbl 74LS18P PDF

    Dual 4-input NAND Schmitt Trigger

    Abstract: M74LS13P M74ls14p 20-PIN
    Text: MITSUBISHI LSTTLs M74LS13P DUAL 4 -IN P U T NAND S C H M ITT TRIGGER DESCRIPTION The M 74LS 13P PIN CONFIGURATION TOP VIEW is a semiconductor integrated circuit containing tw o 4-inp ut positive-logic N A N D gates having a Schm itt trigger function and negative-logic NOR gates.


    OCR Scan     		M74LS13P M74LS13P 16-PIN 20-PIN Dual 4-input NAND Schmitt Trigger M74ls14p PDF

    Untitled

    Abstract: No abstract text available
    Text: MITSUBISHI LSTTLs M74LS13P DUAL 4 -IN P U T NAND S C H M ITT TRIGGER DESCRIPTION The M 74LS 13P PIN CONFIGURATION TOP VIEW is a semiconductor integrated circuit containing tw o 4-inp ut positive-logic N A N D gates having a Schm itt trigger function and negative-logic NOR gates.


    OCR Scan     		M74LS13P b2LHfl27 0013Sbl 14-PIN 16-PIN 20-PIN PDF

    EP1810JC-35

    Abstract: programming manual EP910 EP1810LC-35 OLC-45 EP1810JC35 programming manual EPLD EP1810LI-45 EP1810JC EP1810I Erasable Programmable Logic Device
    Text: EP1810 HIGH-PERFORMANCE 48-MACROCELL ERASABLE PROGRAMMABLE LOGIC DEVICE EPLD D3232. FEBHUARY 1989-REVISED AUGUST 1989 CHIP-CARRIER PACKAGE Erasable, U ser-Configurable LSI Circuit C apable of Implementing 2100 Equivalent Gates of Conventional and Custom Logic


    OCR Scan     		EP1810 48-MACROCELL D3232. 1989-REVISED 33-MHz 68-pin 28Cll EP1810JC-35 programming manual EP910 EP1810LC-35 OLC-45 EP1810JC35 programming manual EPLD EP1810LI-45 EP1810JC EP1810I Erasable Programmable Logic Device PDF