32DIP
Abstract: 32-PIN LH532100B 277A5
Text: LH532100B CMOS 2M 256K x 8 MROM FEATURES DESCRIPTION • 262,144 words × 8 bit organization The LH532100B is a 2M-bit mask-programmable ROM organized as 262,144 × 8 bits. It is fabricated using silicon-gate CMOS process technology. PIN CONNECTIONS 32-PIN DIP
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LH532100B
LH532100B
32-PIN
32QFJ450
32-pin,
450-mil
600-mil
32DIP
277A5
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32DIP
Abstract: 32-PIN LH532100B-1 532100B1-6 timing DIAGRAM OF ROM
Text: LH532100B-1 FEATURES • 262,144 words x 8 bit organization • Access time: 120 ns MAX. • Static operation CMOS 2M (256K × 8) Mask-Programmable ROM PIN CONNECTIONS 32-PIN DIP 32-PIN SOP TOP VIEW OE1/OE1/DC 1 32 VCC A16 2 31 DC • TTL compatible I/O
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LH532100B-1
32-PIN
32QFJ450
32-pin,
450-mil
LH532100B
600-mil
DIP032-P-0600)
32DIP
LH532100B-1
532100B1-6
timing DIAGRAM OF ROM
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32DIP
Abstract: 32-PIN LH532100B CE-2212
Text: LH532100B CMOS 2M 256K x 8 Mask-Programmable ROM FEATURES DESCRIPTION • 262,144 words × 8 bit organization The LH532100B is a 2M-bit mask-programmable ROM organized as 262,144 × 8 bits. It is fabricated using silicon-gate CMOS process technology. PIN CONNECTIONS
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LH532100B
LH532100B
32-PIN
32QFJ450
32-pin,
450-mil
600-mil
32DIP
CE-2212
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32DIP
Abstract: 32-PIN LH532100B-1
Text: LH532100B-1 FEATURES • 262,144 words x 8 bit organization • Access time: 120 ns MAX. • Static operation CMOS 2M (256K × 8) MROM PIN CONNECTIONS 32-PIN DIP 32-PIN SOP TOP VIEW OE1/OE1/DC 1 32 VCC A16 2 31 DC • TTL compatible I/O A15 3 30 A17 4 29
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LH532100B-1
32-PIN
32QFJ450
32-pin,
450-mil
LH532100B
600-mil
DIP032-P-0600)
32DIP
LH532100B-1
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A1SH
Abstract: 32DIP 32-PIN LH532100B-1 A14C
Text: LH532100B-1 FEATURES CMOS 2M 256K x 8 Mask-Programmable ROM PIN CONNECTIONS • 262,144 words x 8 bit organization • Access time: 120 ns (MAX.) 32-PIN DIP 32-PIN SOP TOP VIEW f \ O E ^ O E i/D C C • Static operation • TTL compatible I/O • Three-state outputs
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LH532100B-1
32-pin,
600-miI
525-miI
450-mil
400-mil
A1SH
32DIP
32-PIN
LH532100B-1
A14C
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536G
Abstract: LH534600
Text: MEMORIES • Mask ROMs Process Capacity * Configuration words X bits Pinout Access time Model No. (ns) MIN. Supply current (mA) MAX. Supply voltage (V) (ns) MAX. User's No. Cycle tima Package 256k 32k X 8 J LH53259D/N/T L H 5359X X 150 25 5 ± 10% 28DIP/28SOP/28TSOP(I)
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LH53259D/N/T
LH53517D/N/T/TR
LH531VOOD/N/TAJ
LH53V1ROON/T
LH530800AD/AN/AU
LHS30800AD/AN-Y
LH531OOOBD/BN
LH531000BN-S
LH531024D/N/U
LH532100BD
536G
LH534600
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Untitled
Abstract: No abstract text available
Text: CM O S 2M 256K x 8 Mask-Programmable ROM FEATURES DESCRIPTION • 262,144 x 8 bit organization T h e LH 5 321 00 B is a m ask-program m able R O M organized a s 262,144 x 8 bits. It is fabricated using silicon-gate C M O S p rocess technology. • Access time: 120/150 ns (MAX.)
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32-pin,
600-mil
525-mil
32-PIN
2100B
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Untitled
Abstract: No abstract text available
Text: C M OS 2M 256K x 8 M ask-Program m able ROM FEATURES • 262,144 x 8 bit organization • Access time: 120/150 ns (MAX.) • Low power consumption: Operating: 275 mW (MAX.) DESCRIPTION The LH532100B is a mask-programmable ROM organized as 262,144 x 8 bits. It is fabricated using
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LH532100B
32-pin,
600-mil
525-mil
32-PIN
32-Din,
DIP32-P-600)
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J-1100
Abstract: No abstract text available
Text: LH532100B-1 FEATURES • 262,144 words x 8 bit organization CMOS 2M 256K x 8 MROM PIN CONNECTIONS 32-PIN DIP 32-PIN SOP TOP VIEW • Access time: 120 ns (MAX.) f • Three-state outputs • Single +5 V power supply • Power consumption: Operating: 275 mW (MAX.)
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LH532100B-1
32-PIN
32-pin,
600-mil
525-mil
450-mil
J-1100
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41C1000
Abstract: fujitsu 814100 TC 55464 toshiba HN62304 hn623257 658128 816b 41c464 hn62324 M7202A
Text: MEM ORY ICs FUNCTION GUIDE 3. C R O S S REFERENCE GUIDE 3.1 DRAM Density Org. Samsung Mode Toshiba Hitachi Fujitsu H M 51 256 M B 81256 NEC Oki 64K X 1 Page K M 416 4 25 6 K X 1 F. Page KM 41C256 TC 51256 Nibble KM 41C257 TC51257 S. C olu m n KM 41C258 TC 51258
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41C256
41C257
41C258
41C464
41C466
41C1000
44C256
44C258
44C1002
TC51257
fujitsu 814100
TC 55464 toshiba
HN62304
hn623257
658128
816b
hn62324
M7202A
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DIC14
Abstract: No abstract text available
Text: LH532100B-1 FEATURES • 262,144 words x 8 bit organization • Access time: 120 ns MAX. CMOS 2M (256K x 8) M a sk-P ro g ra m m a b le ROM PIN CONNECTIONS 32-PIN DIP 32-PIN SOP TOP VIEW s • Three-state outputs • Single +5 V power supply • Power consumption:
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LH532100B-1
32-pin,
600-mil
525-mil
450-mil
400-mil
DIC14
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Untitled
Abstract: No abstract text available
Text: CMOS 2M 256K x 8 MROM FEATURES DESCRIPTION • 262,144 w ords x 8 bit organization • Access tim e: 150 ns (MAX.) The LH532100B is a 2M-bit mask-programmable ROM organized as 262,144 x 8 bits. It is fabricated using silicon-gate CMOS process technology.
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32-pin,
600-mil
525-mil
450-mil
400-m
LH532100B
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41C464
Abstract: 41C1000 TC55B8128 424170 NEC CY70199 44C1000 IOT7164 HN62308BP HN62404P TC5116100
Text: MEM ORY ICs CRO SS REFERENCE GUIDE 3. C R O SS REFERENCE GUIDE 3.1 DRAM Density 25 6 K Org. X 1 X 4 1M X 1 X 4 4M X 1 X 4 x8 16M M ode Sa m su n g F. Page KM 41C256 TC 51256 N ibble KM 41C257 TC 51257 S. C o lu m n KM 41C258 TC 51258 H M 51 258 MB81258 F. Page
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41C256
41C257
41C258
41C464
41C466
41C1000
41C1002
44C256
44C258
41C4000
TC55B8128
424170 NEC
CY70199
44C1000
IOT7164
HN62308BP
HN62404P
TC5116100
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K93C46
Abstract: 93cs46n MB832001 hn62308 41C1000 93C46LN 41464 hn623257 HM63832 DT71256
Text: MEMORY ICs CROSS REFERENCE GUIDE 3. CROSS REFERENCE GUIDE 3.1 DRAM D ensity 256K X 1 F. P a g e KM 41C 256 TC 51256 X 1 X 4 4M X 1 X 4 , 1 6M To sh iba M od e X 4 1M Sam su ng Org. H ita ch i Fu jitsu HM 51256 M B81256 NEC /iP D 4 1 2 5 6 N ib b le KM 41C 257
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416C256
14800A
14900A
514170B
514280B
KM23C16000G
KM23C16100G
KM23C16000FP
KM23C16100FP
HN624017FB
K93C46
93cs46n
MB832001
hn62308
41C1000
93C46LN
41464
hn623257
HM63832
DT71256
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lh5359
Abstract: e5bx
Text: Ffe MASK ROM * ★ • MASK ROMs New product Under development * Features • Product lineup covers 11 capacity ranges from 256 k-bit to 128 M-bit. • Product variations with 3 types o f pinout including JEDEC standard EPROM, Mask ROM specific and Flash memory compatible pinout.
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LH-532KXX
LH532100BD/BN/BT/BS/BSR/BU
532048D
53V2P00A
532600D
532000B
532000BD
LH-532C
LH-5326XX
lh5359
e5bx
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DIC20
Abstract: No abstract text available
Text: CMOS 2M 256K x 8 MROM FEATURES DESCRIPTION • 262,144 words x 8 bit organization The LH532100B is a 2M-bit m ask-program m able ROM organized as 262,144 x 8 bits. It is fabricated using silicon-gate CMOS process technology. • Low-power consumption: Operating: 275 mW (MAX.)
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32-pin,
600-mil
525-mil
450-mil
400-mil
LH532100B
DIC20
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capacitor A7C
Abstract: 453J 32TSOP 32DIP 32-PIN A15H LH532100B
Text: CMOS 2M 256K x 8 M ask-Program m able ROM FEATURES DESCRIPTION • 262,144 words x 8 bit organization The LH532100B is a 2M-bit mask-programmable ROM organized as 262,144 x 8 bits. It is fabricated using silicon-gate CMOS process technology. • Access time: 150 ns (MAX.)
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32-pin,
600-mil
525-mil
450-mil
400-mil
LH532100B
capacitor A7C
453J
32TSOP
32DIP
32-PIN
A15H
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500-101
Abstract: No abstract text available
Text: CMOS 2M 256K x 8 Mask-Programmable ROM FEATURES DESCRIPTION • 262,144 words x 8 bit organization The LH532100B is a 2M-bit mask-programmable ROM organized as 262,144 x 8 bits. It is fabricated using silicon-gate CMOS process technology. • Access time: 150 ns (MAX.)
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32-pin,
600-mil
525-mil
450-mil
400-mil
LH532100B
500-101
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ICE ICC3
Abstract: sharp mask rom
Text: CMOS 2M 256K x 8 Mask Programmable ROM FEATURES • 262,144 x 8 bit organization • Access time: 120/150 ns (MAX.) • Low power consumption: DESCRIPTION The LH532100B is a mask programmable ROM organized as 262,144 x 8 bits. It is fabricated using silicon-gate CMOS process technology.
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LH532100B
32-PIN
LH532
32-Din.
600-mil
DIP32-P-600)
32-pin,
525-mil
OP32-P-525)
ICE ICC3
sharp mask rom
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lh5s4
Abstract: LH-MN47XX lh5s4axx LH5359 LH5s lh5317 LH532CXX 32DIP
Text: MEMORIES • JEDEC Standard EPROM Pinout • Low voltage operation 3 V, 1.8 V Access time Bit Capacity configuration 1M 2M 4M Model No. LH53V1ROON/T LH53V2R00AN/AT LH53V2T00E LH53V2YOONÆ LH53V4T00E LH53V4R00AN/AT LH53V4Y00NÆ x 8 x 8 x 8 User’s No. Supply
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LH53V1ROON/T
LH53V2R00AN/AT
LH53V2T00E
LH53V2YOONÆ
LH53V4T00E
LH53V4R00AN/AT
LH53V4Y00NÆ
32SOP/32TSOP
32TSOP
lh5s4
LH-MN47XX
lh5s4axx
LH5359
LH5s
lh5317
LH532CXX
32DIP
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Untitled
Abstract: No abstract text available
Text: LH532100B-1 FEATURES • 262,144 words x 8 bit organization CMOS 2M 256K x 8 MROM PIN CONNECTIONS 32-PIN DIP 32-PIN SOP TOP VIEW • Access time: 120 ns (MAX.) / O E ^Ô Ë ^D C H • Static operation • TTL compatible I/O • Three-state outputs • Power consumption:
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OCR Scan
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PDF
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LH532100B-1
32-PIN
32-pin,
600-mil
525-mil
450-mil
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Untitled
Abstract: No abstract text available
Text: CMOS 2M 256K x 8 Mask-Programmable ROM FEATURES • 2 6 2 ,1 4 4 x 8 bit organization • Access time: 120/150 ns (M AX.) • Low-power consumption: DESCRIPTION The LH532100B is a mask-programmable ROM organized as 262,144 x 8 bits. It is fabricated using
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OCR Scan
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LH532100B
32-pin,
600-m
525-m
32-PIN
32-PtN
600-mil
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