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    16X24

    Abstract: No abstract text available
    Text: QL16x24B/QL16x24BH WildCat 4000 Very-High-Speed 4K 12K Gate CMOS FPGA Rev B pASIC HIGHLIGHTS B Very High Speed - V iaL ink metal-to-metal program m able-via anti­ fuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.


    OCR Scan     		PDF QL16x24B/QL16x24BH 16-by-24 84pin 100-pin 144-pin 160pin 16-bit QL16x24BH 16X24

    QL12x16B

    Abstract: ic 236
    Text: Q L12x16B WildCat 2000 Very-High-Speed 2K 6K Gate CMOS FPGA pASIC HIGHLIGHTS .6000 total available gates, 88 input pins Q Very High Speed - ViaLink metal-to-metal programmable-via anti-fuse technology, allows counter speeds over 150 MHz and logic cell delays of


    OCR Scan     		PDF L12x16B 12-by-16array 68and 84-pin 100-pin QL12xl6 16-bit QL12x16B 12xl6B ic 236

    Untitled

    Abstract: No abstract text available
    Text: QL12x16B W ildCat 2000 Very-High-Speed 2K 6K Gate CMOS FPGA pASIC HIGHLIGHTS Very High Speed - ViaLink metal-to-metal programmable-via anti-fuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns. B High Usable Density - A 12-by-16 array of 192 logic cells provides 6000


    OCR Scan     		PDF QL12x16B 12-by-16 68and 84-pin 100-pin 12xl6 12xl6B

    pl84c

    Abstract: No abstract text available
    Text: QL12x16BL pASIC 1 Family Low Power 3.3 Volt Operation FPGA pASIC HIGHLIGHTS High Speed - ViaLink metal-to-metal program m able-via antifuse technology, allows counter speeds over 80 MHz at 3.3 Volt operation. 5V Tolerant I/Os - Support interface to 5 Volt CMOS, NMOS and


    OCR Scan     		PDF QL12x16BL 12-by-16 68-pin 84-pin 100-pin L12xl6B QL12X16BL-1 PL84C pl84c

    pl68c

    Abstract: No abstract text available
    Text: QL8X12B pASIC 1 Family Very-High-Speed CMOS FPGA Rev B pASIC HIGHLIGHTS S Very High Speed - ViaLink metal-to-metal program m able-via antifuse technology, allows counter speeds over 150 MHz and logic cell delays o f under 2 ns. .1,000 E High Usable Density - An 8-by-12 array of 96 logic cells provides


    OCR Scan     		PDF QL8X12B 8-by-12 44-pin 68-pin 100-pin 16-bit QL8X12B-1 PL68C pl68c

    Untitled

    Abstract: No abstract text available
    Text: Q L16X24B pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS .4,000 usable ASIC gates, 122 I/O pins Very High Speed - ViaLink metal-to-metal program m able-via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.


    OCR Scan     		PDF L16X24B 16-by-24 84-pin 100-pin 144-pin 160-pin 16-bit 16x24B PF144C