Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    HSPICE Search Results

    HSPICE Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    ff1136

    Abstract: MGTRXP0 ROCKETIO UG196 UG351 VIRTEX-5 DS202 UG198 XC5VLX110T-FF1136 XC5VFX70TFF1136 gtx
    Text: Virtex-5 FPGA RocketIO Transceiver Signal Integrity Simulation Kit User Guide for Synopsys HSPICE UG351 v2.2 May 28, 2009 R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development


    Original
    UG351 ff1136 MGTRXP0 ROCKETIO UG196 UG351 VIRTEX-5 DS202 UG198 XC5VLX110T-FF1136 XC5VFX70TFF1136 gtx PDF

    PRBS31

    Abstract: CONN CRD 19 Teradyne connector waveform variable time delay with connector
    Text: Hspice Differential IO Kit User’s Manual Simulation of Lattice SC Product LVDS and other differential Interfaces OVERVIEW The Lattice HSpice IO Kit contains a collection of HSpice model files that allow LVDS and other differential data link simulation across a PCB module or backplane hardware system. Examples of other differential


    Original
    PDF

    Si570

    Abstract: hspice UG366 FPGA Virtex 6 new sis chip
    Text: Virtex-6 FPGA GTX Transceiver Signal Integrity Simulation Kit User Guide for Synopsys HSPICE UG375 v1.1 February 11, 2010 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development


    Original
    UG375 Si570 hspice UG366 FPGA Virtex 6 new sis chip PDF

    hspice

    Abstract: spice simulation EP2S60F1020C3 lo713n Lo713
    Text: I/O Simulations Using HSPICE Writer June 2006, ver. 1.0 Introduction Application Note 424 As edge rates and I/O speeds increase, traditional I/O design methodology such as those methods that use approximate design calculations can no longer guarantee a robust design. Good design


    Original
    PDF

    CONN CRD 19

    Abstract: R1P50 ORSO42G5 ORSO82G5 ORT42G5 ORT82G5 PRBS31
    Text: Hspice CML IO Kit User’s Manual Simulation of Lattice SC and ORCA Product CML SERDES Interfaces OVERVIEW The Lattice HSpice IO Kit contains a collection of HSpice model files that allow SERDES serial data link simulation across a PCB module or backplane hardware system. The SERDES buffer models are extracted


    Original
    PDF

    flyback

    Abstract: Average simulations of FLYBACK converters with SPICE3 UC3845 pspice model SEM-800 dixon flyback smps uc3845 UC3845 spice model SUBCKT XFMR 1 2 3 4. RP 1 2 1MEG voltage controlled pwm generator 0 to 100 pspice model uc3845 isolated smps Spice model xfmr
    Text: Average simulations of FLYBACK converters with SPICE3 Christophe BASSO May 1996 Within the wide family of Switch Mode Power Supplies SMPS , the Flyback converter represents the preferred structure for use in small and medium power applications such as wall


    Original
    PDF

    Untitled

    Abstract: No abstract text available
    Text: MAX3785 Output Model 6.25Gbps 1.8V Board Equalizer SPICE I/O Macromodels aid in understanding signal integrity issues in electronic systems. Most of Maxim’s High Frequency/Fiber Communication ICs utilize input and output I/O circuits with Current Mode Logic (CML), Positive Emitter Coupled Logic


    Original
    MAX3785 25Gbps worst-c28 REPORTERL1N29 REPORTERL1N30 920E-018 DE0900A DE0396 REPORTERL1N27 REPORTERL1N28 PDF

    MICRON BGA PART MARKING

    Abstract: No abstract text available
    Text: 288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM 2 Features CIO RLDRAM 2 MT49H32M9 – 32 Meg x 9 x 8 Banks MT49H16M18 – 16 Meg x 18 x 8 Banks MT49H8M36 – 8 Meg x 36 x 8 Banks Features Options1 • 533 MHz DDR operation 1.067 Gb/s/pin data rate


    Original
    288Mb: MT49H32M9 MT49H16M18 MT49H8M36 09005aef80a41b46/Source: 09005aef809f284b MICRON BGA PART MARKING PDF

    ep4cgx30f484

    Abstract: EP4CE115 CYIV-5V1-1 EP4CGX EP4CE55 EP4CE15 sigma delta lcd screen lvds 40 pin diagram ep4ce22 ep4ce40
    Text: Cyclone IV Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com CYIV-5V1-1.5 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other


    Original
    PDF

    msi 7267 MOTHERBOARD SERVICE MANUAL

    Abstract: ttl cookbook msi ms 7267 MOTHERBOARD CIRCUIT diagram "0.4mm" bga "ball collapse" height PCF 799 crystal oscillator 8MHz 4 pins smd diode MARKING F5 44C smd TRANSISTOR code marking A7 terminals diagram of smd transistor bo2 cookbook for ic 555
    Text: GTL/GTLP Logic High-Performance Backplane Drivers Data Book Printed on Recycled Paper IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information


    Original
    GDFP1-F48 -146AA GDFP1-F56 -146AB msi 7267 MOTHERBOARD SERVICE MANUAL ttl cookbook msi ms 7267 MOTHERBOARD CIRCUIT diagram "0.4mm" bga "ball collapse" height PCF 799 crystal oscillator 8MHz 4 pins smd diode MARKING F5 44C smd TRANSISTOR code marking A7 terminals diagram of smd transistor bo2 cookbook for ic 555 PDF

    G T 3H

    Abstract: 44-QFP S3C9688 S3P9688 SAM88RCRI
    Text: S3C9688/P9688 1 PRODUCT OVERVIEW PRODUCT OVERVIEW SAM88RCRI PRODUCT FAMILY Samsung's SAM88RCRI family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes.


    Original
    S3C9688/P9688 SAM88RCRI S3C9688/P9688 42-Pin 50-Pin AP42SD-J) SM6524 G T 3H 44-QFP S3C9688 S3P9688 PDF

    IBM0418A8ACLAB

    Abstract: IBM0436A4ACLAB IBM0436A8ACLAB IBM0418A4ACLAB
    Text: . IBM0418A4ACLAB IBM0436A8ACLAB Preliminary IBM0418A8ACLAB IBM0436A4ACLAB 8Mb 256Kx36 & 512Kx18 and 4Mb (128Kx36 & 256Kx18) SRAM Features • 8Mb: 256K x 36 or 512K x 18 organizations 4Mb: 128K x 36 or 256K x 18 organizations • 0.25 Micron CMOS technology


    Original
    IBM0418A4ACLAB IBM0436A8ACLAB IBM0418A8ACLAB IBM0436A4ACLAB 256Kx36 512Kx18) 128Kx36 256Kx18) crlh3320 IBM0418A8ACLAB IBM0436A4ACLAB IBM0436A8ACLAB IBM0418A4ACLAB PDF

    3S400

    Abstract: 3S200 visionprobe 2V250 V600 3S50 3S400 ibis DIAB ISE BASEX MXE
    Text: Devices Design Entry Embedded System Design Synthesis Feature ISE WebPACK ISE BaseX ISE Foundation ISE Alliance Virtex Series Virtex-E: V50E -V300E Virtex-II: 2V40 - 2V250 Virtex-II Pro: 2VP2 Virtex: V50 - V600 Virtex-E: V50E - V600E Virtex-II: 2V40 - 2V500


    Original
    -V300E 2V250 V600E 2V500 XC2S400E XC2S600E) 3S200, 3S400 3S400 3S200 visionprobe 2V250 V600 3S50 3S400 ibis DIAB ISE BASEX MXE PDF

    OC48

    Abstract: SSTL-15 SSTL-18
    Text: Arria II Device Handbook Volume 3: Device Datasheet and Addendum Arria II Device Handbook Volume 3: Device Datasheet and Addendum 101 Innovation Drive San Jose, CA 95134 www.altera.com AIIGX5V3-4.0 Document last updated for Altera Complete Design Suite version:


    Original
    PDF

    H12A05

    Abstract: No abstract text available
    Text: MAX3269 I/O Model SPICE I/O Macromodels aid in understanding signal integrity issues in electronic systems. Most of Maxim’s High Frequency/Fiber Communication ICs utilize input and output I/O circuits with Current Mode Logic (CML), Positive Emitter Coupled Logic (PECL), and Low


    Original
    MAX3269 testi509 326E-017 573E-020 022E-029 968E-018 H14E04 H12A05 PDF

    1P NPN

    Abstract: TC227 AX3910
    Text: MAX3910u/d Output Model SPICE I/O Macromodels aid in understanding signal integrity issues in electronic systems. Most of Maxim’s High Frequency/Fiber Communication ICs utilize input and output I/O circuits with Current Mode Logic (CML), Positive Emitter Coupled Logic


    Original
    MAX3910u/d DE0172 PADESD25 DE0172 514E-018 1P NPN TC227 AX3910 PDF

    max3963

    Abstract: No abstract text available
    Text: MAX3963CSA Output Model SPICE I/O Macromodels aid in understanding signal integrity issues in electronic systems. Most of Maxim’s High Frequency/Fiber Communication ICs utilize input and output I/O circuits with Current Mode Logic (CML), Positive Emitter Coupled Logic (PECL), and Low Voltage Differential Signal (LVDS)


    Original
    MAX3963CSA 151E-017 444E-021 000E-030 540E-019 H11A05 max3963 PDF

    npn TTL LOGIC pspice model

    Abstract: vcsel spice model
    Text: MAX3905 Input Model SPICE I/O Macromodels aid in understanding signal integrity issues in electronic systems. Most of Maxim’s High Frequency/Fiber Communication ICs utilize input and output I/O circuits with Current Mode Logic (CML), Positive Emitter Coupled Logic


    Original
    MAX3905 teH21M02 HDE072021 591E-018 HDE072021 npn TTL LOGIC pspice model vcsel spice model PDF

    c4001 transistor

    Abstract: transistor c4001 k0203 TC182 3004 transistor
    Text: MAX3885ECB Input Model SPICE I/O Macromodels aid in understanding signal integrity issues in electronic systems. Most of Maxim’s High Frequency/Fiber Communication ICs utilize input and output I/O circuits with Current Mode Logic (CML), Positive Emitter Coupled Logic (PECL), and Low


    Original
    MAX3885ECB for61 151E-017 444E-021 000E-030 540E-019 H11A05 c4001 transistor transistor c4001 k0203 TC182 3004 transistor PDF

    TC227

    Abstract: No abstract text available
    Text: MAX3935 I/O Model SPICE I/O Macromodels aid in understanding signal integrity issues in electronic systems. Most of Maxim’s High Frequency/Fiber Communication ICs utilize input and output I/O circuits with Current Mode Logic (CML), Positive Emitter Coupled Logic


    Original
    MAX3935 DE0172 PADESD25 DE0172 514E-018 TC227 PDF

    vcsel spice model

    Abstract: No abstract text available
    Text: MAX3996 I/O Model 2.5Gbps VCSEL Driver SPICE I/O Macromodels aid in understanding signal integrity issues in electronic systems. Most of Maxim’s High Frequency/Fiber Communication ICs utilize input and output I/O circuits with Current Mode Logic (CML), Positive Emitter Coupled Logic (PECL), and


    Original
    MAX3996 920E-018 083E-022 168E-030 680E-019 H11A02 vcsel spice model PDF

    75188N

    Abstract: LED pspice model
    Text: MAX3966 Input Model SPICE I/O Macromodels aid in understanding signal integrity issues in electronic systems. Most of Maxim’s High Frequency/Fiber Communication ICs utilize input and output I/O circuits with Current Mode Logic (CML), Positive Emitter Coupled Logic


    Original
    MAX3966 N11A03 22809e-13 29926e-14 113E-17 3397e-13 81509e-14 75188N LED pspice model PDF

    Untitled

    Abstract: No abstract text available
    Text: MAX3804 I/O Model 10Gbps Equalizer SPICE I/O Macromodels aid in understanding signal integrity issues in electronic systems. Most of Maxim’s High Frequency/Fiber Communication ICs utilize input and output I/O circuits with Current Mode Logic (CML), Positive Emitter Coupled Logic (PECL), and Low Voltage Differential Signal


    Original
    MAX3804 10Gbps REPORTERL1N11 REPORTERL1N12 926E-018 463E-018 558E-030 N102M066 PDF

    TC227

    Abstract: N102M024
    Text: MAX3735 I/O Model SPICE I/O Macromodels aid in understanding signal integrity issues in electronic systems. Most of Maxim’s High Frequency/Fiber Communication ICs utilize input and output I/O circuits with Current Mode Logic (CML), Positive Emitter Coupled Logic


    Original
    MAX3735 558E-018 279E-018 N102M024 TC227 N102M024 PDF