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    HSP50214 Search Results

    HSP50214 Result Highlights (4)

    Part ECAD Model Manufacturer Description Download Buy
    HSP50214BVI Renesas Electronics Corporation Programmable Downconverter, MQFP-HS, /Tray Visit Renesas Electronics Corporation
    HSP50214BVC Renesas Electronics Corporation Programmable Downconverter, MQFP-HS, /Tray Visit Renesas Electronics Corporation
    HSP50214BVIZ Renesas Electronics Corporation Programmable Downconverter Visit Renesas Electronics Corporation
    HSP50214BVCZ Renesas Electronics Corporation Programmable Downconverter Visit Renesas Electronics Corporation
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    HSP50214 Price and Stock

    Renesas Electronics Corporation HSP50214BVCZ

    IC DOWNCONVERTER 14BIT 120-MQFP
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    DigiKey HSP50214BVCZ Tray
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    Avnet Americas HSP50214BVCZ Tray 4 Weeks 5
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    Rochester Electronics HSP50214BVCZ 845 1
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    Renesas Electronics Corporation HSP50214AVC

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    Avnet Americas HSP50214AVC Bulk 4 Weeks 11
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    Renesas Electronics Corporation HSP50214BVI

    Programmable Downconverter 120-Pin MQFP - Trays (Alt: HSP50214BVI)
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    Avnet Americas HSP50214BVI Tray 4 Weeks 2
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    Renesas Electronics Corporation HSP50214VC

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    Renesas Electronics Corporation HSP50214VI

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    HSP50214 Datasheets (26)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    HSP50214 Harris Semiconductor ST-114 Harris HSP50214 Downconverter Evaluation Board Original PDF
    HSP50214 Harris Semiconductor Original PDF
    HSP50214 Harris Semiconductor Programmable Downconverter Original PDF
    hsp50214 Intersil Obsolete Product Datasheet Original PDF
    HSP50214A Intersil Programmable Downconverter Original PDF
    HSP50214AVC Intersil Programmable Downconverter Original PDF
    HSP50214AVI Intersil Programmable Downconverter Original PDF
    HSP50214B Intersil Programmable Downconverter Original PDF
    HSP50214BVC Intersil Calculating Maximum Processing Rates of the PDC (HSP50214, HSP50214A and HSP50214B) Original PDF
    HSP50214BVC Intersil Programmable Downconverter Original PDF
    HSP50214BVC Intersil Serinade License And Tutorial Original PDF
    HSP50214BVC Intersil ST-114 Intersil HSP50214 Downconverter Evaluation Board (Sigtek 410-290-3918) Original PDF
    HSP50214BVC Intersil Calculating the Maximum Output Sample Rate and Bandwidth Specifications of the HSP50214 Original PDF
    HSP50214BVC Intersil Programmable Downconverter; Temperature Range: 0°C to 70°C; Package: 120-MQFP Original PDF
    HSP50214BVC Intersil Programmable Downconverter Original PDF
    HSP50214BVCZ Intersil Programmable Downconverter Original PDF
    HSP50214BVI Intersil Serinade License And Tutorial Original PDF
    HSP50214BVI Intersil Calculating Maximum Processing Rates of the PDC (HSP50214, HSP50214A and HSP50214B) Original PDF
    HSP50214BVI Intersil Programmable Downconverter Original PDF
    HSP50214BVI Intersil Calculating the Maximum Output Sample Rate and Bandwidth Specifications of the HSP50214 Original PDF

    HSP50214 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Tuner sharp QPSK

    Abstract: 9031 code fir filter Numerically Controlled Oscillator HSP50210 HSP50214 HSP50214VC HSP50214VI
    Text: February 2000 Programmable Downconverter Features Description • Up to 52 MSPS Front-End Processing Rates CLKIN and 35 MSPS Back-End Processing Rates (PROCCLK) Clocks May Be Asynchronous The HSP50214 Programmable Downconverter converts digitized IF data into filtered baseband data which can be


    Original     		PDF HSP50214 100dB 255-Tap 625kHz Tuner sharp QPSK 9031 code fir filter Numerically Controlled Oscillator HSP50210 HSP50214VC HSP50214VI

    CIC interpolation Filter

    Abstract: HSP50214 HSP50214A HSP50214B TB349 cic filter
    Text: Calculating the Maximum Output Sample Rate and Bandwidth Specifications of the HSP50214 TM Technical Brief January 1998 TB349.1 Authors: John Henkelman and David Damerow Output Sample Rate and Bandwidth Specifications Calculating the Output Rate • Output Samples at 6.6 MSPS with Output Bandwidths


    Original     		PDF HSP50214 TB349 500kHz 625kHz HSP50214 982kHz HSP50214A CIC interpolation Filter HSP50214B cic filter

    tuner 3402

    Abstract: HSP50210 HSP50214B HSP50214BVC HSP50214BVI
    Text: HSP50214B Semiconductor Data Sheet February 1999 File Number 4450.2 Programmable Downconverter Features The HSP50214B Programmable Downconverter converts digitized IF data into filtered baseband data which can be processed by a standard DSP microprocessor. The


    Original     		PDF HSP50214B HSP50214B 55MHz 14-bit tuner 3402 HSP50210 HSP50214BVC HSP50214BVI

    Untitled

    Abstract: No abstract text available
    Text: HSP50214B S E M I C O N D U C T O R Programmable Downconverter February 1998 Features Description • Up to 65 MSPS Front-End Processing Rates CLKIN and 55MHz Back-End Processing Rates (PROCCLK) Clocks May Be Asynchronous • Processing Capable of >100dB SFDR


    Original     		PDF HSP50214B HSP50214B 14-bit 255-ts 1-800-4-HARRIS

    96330

    Abstract: No abstract text available
    Text: HSP50214A S E M I C O N D U C T O R Programmable Downconverter February 1998 Features Description • Up to 65 MSPS Front-End Processing Rates CLKIN and 55 MSPS (41 MSPS Using the Discriminator) Back-End Processing Rates (PROCCLK) Clocks May Be Asynchronous


    Original     		PDF HSP50214A HSP50214A 14-bit 255-RL 96330

    16 AS 15 HB1

    Abstract: No abstract text available
    Text: Calculating Maximum Processing Rates of the PDC HSP50214, HSP50214A and HSP50214B Application Note January 1999 AN9720.2 Authors: John Henkelman and Dave Damerow Introduction [ /Title (AN97 20) /Subject (Calculating Maximum Processing Rates of the PDC (HSP5


    Original     		PDF HSP50214, HSP50214A HSP50214B) AN9720 HSP50 16 AS 15 HB1

    cic filter

    Abstract: decimation filters HSP50214 logic diagram of ic 7432 DC variable power center tap HB2-0 HSP50214A HSP50214B
    Text: Calculating Maximum Processing Rates of the PDC HSP50214, HSP50214A and HSP50214B Application Note Introduction January 1999 AN9720.2 BAND OF INTEREST Configuring the Programmable Digital Downconverter (PDC) requires selecting clock, decimation and interpolation rates for


    Original     		PDF HSP50214, HSP50214A HSP50214B) AN9720 cic filter decimation filters HSP50214 logic diagram of ic 7432 DC variable power center tap HB2-0 HSP50214B

    cic filter

    Abstract: HSP50214 HSP50214A HSP50214B cic filter for digital down converter
    Text: TM Calculating Maximum Processing Rates of the PDC HSP50214, HSP50214A and HSP50214B Application Note January 1999 Introduction AN9720.2 BAND OF INTEREST Configuring the Programmable Digital Downconverter (PDC) requires selecting clock, decimation and interpolation rates for


    Original     		PDF HSP50214, HSP50214A HSP50214B) AN9720 cic filter HSP50214 HSP50214B cic filter for digital down converter

    HSP50210

    Abstract: HSP50214B HSP50214BVI SAMPO intersil application note book CORDIC QAM modulation Tuner sharp QPSK
    Text: HSP50214B TM Data Sheet May 2000 File Number 4450.3 Programmable Downconverter Features The HSP50214B Programmable Downconverter converts • Up to 65 MSPS Front-End Processing Rates CLKIN and 55MHz Back-End Processing Rates (PROCCLK) Clocks May Be Asynchronous


    Original     		PDF HSP50214B HSP50214B 55MHz 255-TAP 100dB 255-Tap 982kHz 32-Bit HSP50210 HSP50214BVI SAMPO intersil application note book CORDIC QAM modulation Tuner sharp QPSK

    Tuner sharp BPSK

    Abstract: 16 bit parallel to serial NMT-900 HSP50214 HSP50214VC HSP50214VI HSP50210 polar modulator 3122 adj
    Text: HSP50214 S E M I C O N D U C T O R Programmable Downconverter February 1998 Features Description • Up to 52 MSPS Front-End Processing Rates CLKIN and 35 MSPS Back-End Processing Rates (PROCCLK) Clocks May Be Asynchronous The HSP50214 Programmable Downconverter converts


    Original     		PDF HSP50214 HSP50214 100dB 255-Tap 1-800-4-HARRIS Tuner sharp BPSK 16 bit parallel to serial NMT-900 HSP50214VC HSP50214VI HSP50210 polar modulator 3122 adj

    cic filter

    Abstract: cic filter for digital down converter decimation filters transistor 9720 HSP50214 cic2852 AN9720
    Text: Harris Semiconductor No. AN9720 Digital Signal Processing June 1997 Calculating Maximum Processing Rates of the PDC HSP50214 Authors: John Henkelman and Dave Damerow Introduction cess a lower frequency sampling alias of the IF signal should be considered. If the IF is in the lower portion of the A/D


    Original     		PDF AN9720 HSP50214) HSP50214 cic filter cic filter for digital down converter decimation filters transistor 9720 cic2852 AN9720

    TB349

    Abstract: HSP50214 Resampler sample rate
    Text: Harris Semiconductor No. TB349 Digital Signal Processing June 1997 Calculating the Maximum Output Sample Rate and Bandwidth of the HSP50214 Authors: John Henkelman and David Damerow Output Sample Rate and Bandwidth Specifications interpolation filters is 35MHz/17 = 2.059MHz 28MHz/17 =


    Original     		PDF TB349 HSP50214 35MHz/17 059MHz 28MHz/17 647MHz) 500kHz 625kHz 28MHz/7 52MHz/7 TB349 HSP50214 Resampler sample rate

    cic filter

    Abstract: HSP50214 HSP50214A HSP50214B ASSP29 circuit diagram for FIR filter
    Text: Calculating Maximum Processing Rates of the PDC HSP50214, HSP50214A and HSP50214B Application Note January 1999 AN9720.2 Authors: John Henkelman and Dave Damerow Introduction BAND OF INTEREST Configuring the Programmable Digital Downconverter (PDC) requires selecting clock, decimation and interpolation rates for


    Original     		PDF HSP50214, HSP50214A HSP50214B) AN9720 cic filter HSP50214 HSP50214B ASSP29 circuit diagram for FIR filter

    TMS320C50 specifications

    Abstract: tms320c50 ST 9841 harris CA3338A HI5703 HSP45106 HSP50214 ST-114 FSK bit error rate
    Text: SIGTEK I N C O R P O R A T E D ST-114 Harris HSP50214 Downconverter Evaluation Board The ST-114 is a flexible PC/AT ISA bus evaluation platform for the Harris HSP50214 Programmable Downconverter. Within a matter of minutes after installation in a PC, the ST-114 is up and running. The board simultaneously generates and


    Original     		PDF ST-114 HSP50214 TMS320C50 TMS320C50 specifications ST 9841 harris CA3338A HI5703 HSP45106 FSK bit error rate

    HSP50214

    Abstract: HSP50214A HSP50214B TB349 cic filter
    Text: Calculating the Maximum Output Sample Rate and Bandwidth Specifications of the HSP50214 Technical Brief January 1998 TB349.1 Authors: John Henkelman and David Damerow Output Sample Rate and Bandwidth Specifications • Output Samples at 6.6 MSPS with Output Bandwidths to


    Original     		PDF HSP50214 TB349 500kHz 625kHz HSP50214 982kHz HSP50214A HSP50214B cic filter

    Untitled

    Abstract: No abstract text available
    Text: HSP50214 HARRIS S E M I C O N D U C T O R Programmable Downconverter February 1998 Features Description • Up to 52 MSPS Front-End Processing Rates CLKIN and 35 MSPS Back-End Processing Rates (PROCCLK) Clocks May Be Asynchronous The HSP50214 Programmable Downconverter converts


    OCR Scan     		PDF HSP50214 HSP50214 100dB 255-Tap 1-800-4-HARRIS

    Untitled

    Abstract: No abstract text available
    Text: HSP50214B Semiconductor Data Sheet January 1999 4450.1 File Number Programmable Downconverter Features The HSP50214B Programmable Downconverter converts digitized IF data into filtered baseband data which can be processed by a standard DSP microprocessor. The


    OCR Scan     		PDF HSP50214B HSP50214B 55MHz 14-bit

    TMS320C50

    Abstract: No abstract text available
    Text: ST-114 Product Sheet The board Is controlled through a Windows interface which allows full access to all HSP50214 registers, and provides controls and displays for FM, FSK, BPSK and QPSK signal demodulation. To speed evaluation, the ST-114 includes a Harris HI5703 10 Bit 40


    OCR Scan     		PDF ST-114 HSP50214 ST114 HI5703 HSP45106 TMS320C50

    cic filter for digital down converter

    Abstract: No abstract text available
    Text: ¡33 M A fiE S » HSP50214 ADVANCE INFORMATION November 1996 Programmable Downconverter Features Description • Up to 52 MSPS Input The HSP50214 Programmable Downconverter converts digitized IF data into data which can be processed by the standard DSP microprocessor. At least 14 bits of dynamic


    OCR Scan     		PDF 32-Bit 100dB 500kHz 16-Bit HSP50210 HI5805 HI5703 HSP50214VC HSP50214VI 28x28 cic filter for digital down converter

    Untitled

    Abstract: No abstract text available
    Text: HSP50214B Semiconductor Data Sheet January 1999 4450.1 File Number Programmable Downconverter Features The HSP50214B Programmable Downconverter converts digitized IF data into filtered baseband data which can be processed by a standard DSP microprocessor. The


    OCR Scan     		PDF HSP50214B HSP50214B 55MHz 14-bit

    pdc 7ro

    Abstract: FEC15 ix 3394
    Text: HSP50214B Semiconductor D a ta s h e e t F e b ru a ry 1999 F ile N u m b e r 4450.2 Programmable Downconverter Features The HSP50214B Programmable Downconverter converts digitized IF data into filtered baseband data which can be processed by a standard DSP microprocessor. The


    OCR Scan     		PDF HSP50214B HSP50214B 14-bit pdc 7ro FEC15 ix 3394

    832 fm

    Abstract: No abstract text available
    Text: fÇj HARRIS HSP50214 S E M I C O N D U C T O R Programmable Downconverter February 1998 Features Description • Up to 52 M S P S F ront-E nd P ro cessin g R ates C L K IN and 35 M S P S B ack-E nd Pro cessin g Rates (P R O C C L K ) C locks M ay Be A s yn ch ro n o u s


    OCR Scan     		PDF HSP50214 HSP50214 14-bit 40MHz 28MHz 500kHz 500kHz. 832 fm

    HSP50214BVC

    Abstract: No abstract text available
    Text: fÇ j H A R R H S P 50214B IS S E M I C O N D U C T O R Programmable Downconverter February 1998 Features Description • Up to 65 MSPS Front-End Processing Rates CLKIN and 55MHz Back-End Processing Rates (PROCCLK) Clocks May Be Asynchronous The HSP50214B Programmable Downconverter converts


    OCR Scan     		PDF 50214B HSP50214B 14-bit 40MHz 28MHz 500kHz 500kHz. HSP50214BVC

    Untitled

    Abstract: No abstract text available
    Text: i ? i? ic Sem iconductor | Calculating the Maximum Output Sample Rate and Bandwidth Specifications of the HSP50214 T e c h n ic a l B n e l J a n u a ry 1998 TB 349.1 Authors: John Henkelman and David Damerow Output Sample Rate and Bandwidth Specifications


    OCR Scan     		PDF HSP50214 500kHz 625kHz HSP50214 982kHz HSP50214A HSP50214B 55MHz 857MHz