Untitled
Abstract: No abstract text available
Text: Preliminary GS8342T07/10/19/37BD-450/400/350/333/300 36Mb SigmaDDR-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package
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Original
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GS8342T07/10/19/37BD-450/400/350/333/300
165-Bump
GS8342T37BGD-300I
GS8342TxxBD-333T.
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PDF
|
Untitled
Abstract: No abstract text available
Text: Preliminary GS8342T08/09/18/36BD-400/350/333/300/250 36Mb SigmaDDR-IITM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 400 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus
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Original
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GS8342T08/09/18/36BD-400/350/333/300/250
165-Bump
165-bump,
GS8342Tx36BD-300T.
|
PDF
|
Untitled
Abstract: No abstract text available
Text: GS8342T08/09/18/36AE-300M 165-Bump BGA Military Temp 36Mb SigmaCIO DDR-II Burst of 2 SRAM 300 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Military Temperature Range • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus • JEDEC-standard pinout and package
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Original
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GS8342T08/09/18/36AE-300M
165-Bump
165-bump,
144Mb
GS8342T08AE-300M
GS8342T09AE-300M
GS8342T18AE-300M
GS8342T36AE-300M
165-Pin
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PDF
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Untitled
Abstract: No abstract text available
Text: GS8342T08/09/18/36AE-333/300/250/200/167 36Mb SigmaDDR-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaDDR-II™ Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface
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Original
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GS8342T08/09/18/36AE-333/300/250/200/167
165-Bump
165-bump,
GS8342TxxA
|
PDF
|
Untitled
Abstract: No abstract text available
Text: GS8342T08/09/18/36BD-400/350/333/300/250 36Mb SigmaDDR-IITM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface
|
Original
|
GS8342T08/09/18/36BD-400/350/333/300/250
165-Bump
165-bump,
|
PDF
|
Untitled
Abstract: No abstract text available
Text: Preliminary GS8342T08/09/18/36BD-400/350/333/300/250 36Mb SigmaDDR-IITM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 400 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus
|
Original
|
GS8342T08/09/18/36BD-400/350/333/300/250
165-Bump
165-bump,
GS8342Tx36BD-300T.
|
PDF
|
Untitled
Abstract: No abstract text available
Text: Preliminary GS8342T08/09/18/36AE-333/300/250/200/167 36Mb SigmaCIO DDR-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus
|
Original
|
GS8342T08/09/18/36AE-333/300/250/200/167
165-Bump
165-bump,
m834x36E-300T.
GS8342TxxA
|
PDF
|
Untitled
Abstract: No abstract text available
Text: GS8342T08/09/18/36AE-300M 165-Bump BGA Military Temp 36Mb SigmaDDR-II Burst of 2 SRAM Features • Military Temperature Range • Simultaneous Read and Write SigmaDDR-II™ Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface
|
Original
|
GS8342T08/09/18/36AE-300M
165-Bump
165-bump,
GS8342T09AE-300M
165-Pin
GS8342T18AE-300M
GS8342T36AE-300M
GS8342T36AE-300MT.
|
PDF
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AN1019
Abstract: No abstract text available
Text: AN1019 SigmaQuad-II+ and SigmaDDR-II+ On-Die Termination ODT Introduction When an electrical signal is transmitted along a transmission line, it is reflected back when it reaches the end of the line. That reflection induces noise which adversely affects the quality of the signal, thereby making it more difficult for the receiving device
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Original
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AN1019
AN1019
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PDF
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Untitled
Abstract: No abstract text available
Text: GS8342T08/09/18/36AE-333/300/250/200/167 36Mb SigmaCIO DDR-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus • JEDEC-standard pinout and package
|
Original
|
GS8342T08/09/18/36AE-333/300/250/200/167
165-Bump
165-bump,
144Mbiver
GS8342TxxA
|
PDF
|
Untitled
Abstract: No abstract text available
Text: GS8342T07/10/19/37BD-450/400/350/333/300 36Mb SigmaDDR-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package
|
Original
|
GS8342T07/10/19/37BD-450/400/350/333/300
165-Bump
165-bump,
GS8342TxxBD-333T.
|
PDF
|
Untitled
Abstract: No abstract text available
Text: GS8342T08/09/18/36BD-400/350/333/300/250 36Mb SigmaDDR-IITM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface
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Original
|
GS8342T08/09/18/36BD-400/350/333/300/250
165-Bump
165-bump,
36MIndustrial
|
PDF
|
Untitled
Abstract: No abstract text available
Text: GS8342T08/09/18/36AE-300M 165-Bump BGA Military Temp 36Mb SigmaDDR-II Burst of 2 SRAM Features • Military Temperature Range • Simultaneous Read and Write SigmaDDR-II™ Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface
|
Original
|
GS8342T08/09/18/36AE-300M
165-Bump
165-bump,
144Mb
a342T08AE-300M
GS8342T09AE-300M
GS8342T18AE-300M
GS8342T36AE-300M
165-Pin
|
PDF
|
Untitled
Abstract: No abstract text available
Text: Preliminary GS8342T08/09/18/36BD-400/350/333/300/250 36Mb SigmaDDR-IITM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface
|
Original
|
GS8342T08/09/18/36BD-400/350/333/300/250
165-Bump
165-bump,
|
PDF
|
|
|
GS8342T36BGD-250
Abstract: No abstract text available
Text: Preliminary GS8342T08/09/18/36BD-400/350/333/300/250 36Mb SigmaDDR-IITM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface
|
Original
|
GS8342T08/09/18/36BD-400/350/333/300/250
165-Bump
165-bump,
GS8342Tx36BD-300T.
GS8342T36BGD-250
|
PDF
|
Untitled
Abstract: No abstract text available
Text: GS8342T08/09/18/36AE-333/300/250/200/167 36Mb SigmaDDR-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaDDR-II™ Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface
|
Original
|
GS8342T08/09/18/36AE-333/300/250/200/167
165-Bump
165-bump,
165-b2TxxA
GS8342TxxA
|
PDF
|
Untitled
Abstract: No abstract text available
Text: Preliminary GS8342T08/09/18/36E-333/300/267*/250/200/167 36Mb SigmaCIO DDR-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus
|
Original
|
GS8342T08/09/18/36E-333/300/267
165-Bump
165-bump,
GS8342Txx
|
PDF
|
Untitled
Abstract: No abstract text available
Text: Preliminary GS8342T07/10/19/37BD-450/400/350/333/300 36Mb SigmaDDR-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 450 MHz–300 MHz 1.8 V VDD 1.8 V or 1.5 V I/O Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface
|
Original
|
GS8342T07/10/19/37BD-450/400/350/333/300
165-Bump
165-bump,
GS8342TxxBD-333T.
|
PDF
|
Untitled
Abstract: No abstract text available
Text: Preliminary GS8342T07/10/19/37BD-450/400/350/333/300 36Mb SigmaDDR-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 450 MHz–300 MHz 1.8 V VDD 1.8 V or 1.5 V I/O Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface
|
Original
|
GS8342T07/10/19/37BD-450/400/350/333/300
165-Bump
165-bump,
GS8342TxxBD-333T.
|
PDF
|
Untitled
Abstract: No abstract text available
Text: Preliminary GS8342T08/09/18/36AE-333/300/250/200/167 36Mb SigmaCIO DDR-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus
|
Original
|
GS8342T08/09/18/36AE-333/300/250/200/167
165-Bump
165-bump,
GS834x36E-300T.
GS8342TxxA
|
PDF
|
Untitled
Abstract: No abstract text available
Text: GS8342T07/10/19/37BD-450/400/350/333/300 36Mb SigmaDDR-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package
|
Original
|
GS8342T07/10/19/37BD-450/400/350/333/300
165-Bump
I2T37BGD-300I
GS8342TxxBD-333T.
|
PDF
|
GS8342T36AGE-200
Abstract: GS8342T36AE-300I GS8342T36AGE-250 GS8342T36AE-250
Text: Preliminary GS8342T08/09/18/36AE-333/300/250/200/167 36Mb SigmaCIO DDR-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus
|
Original
|
GS8342T08/09/18/36AE-333/300/250/200/167
165-Bump
165-bump,
GS8342TxxA
GS8342T36AGE-200
GS8342T36AE-300I
GS8342T36AGE-250
GS8342T36AE-250
|
PDF
|
GS8342T36AE-250
Abstract: GS8342T36AGE-200 GS8342T36 GS8342T36AGE
Text: GS8342T08/09/18/36AE-333/300/250/200/167 36Mb SigmaCIO DDR-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus • JEDEC-standard pinout and package
|
Original
|
GS8342T08/09/18/36AE-333/300/250/200/167
165-Bump
165-bump,
GS8342TxxA
GS8342T36AE-250
GS8342T36AGE-200
GS8342T36
GS8342T36AGE
|
PDF
|