MDD 1654
Abstract: TMT Isolator wr 90 x band flange waveguide teledyne yig oscillator 10GHz bandpass filter yig oscillator hp m7928 teledyne microwave mbg ferretec filtronic band-pass
Text: TELEDYNEMICROWAVE the complete microwave solution Table of Contents Company Profile. . . . . . . . . . . . . . . . . . . . . . . . . 5 Sub-Systems. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Diplexers and Multiplexers. . . . . . . . . . . . . . . . . . . . . . . . . . 82
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74F1056
Abstract: 74F1056SC C1995 M16A b50 diode
Text: F1056 8-Bit Schottky Barrier Diode Array General Description Features The ’F1056 is an 8-bit Schottky barrier diode array designed to be employed as termination on the inputs to memory bus lines or CLOCK lines This device is designed to suppress negative transients caused by line reflections switching
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74F1056
F1056
74F1056SC
16-Lead
74F1056
74F1056SC
C1995
M16A
b50 diode
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F10166
Abstract: F10566
Text: F10166^ F10566 5-BIT COMPARATOR F10K VOLTAGE COMPENSATED ECL DESCRIPTION - The F10166/F10566 are high-speed expandable 5-Bit Comparators for comparing the magnitude of two binary words. Two outputs are provided: A>B and A<B. A = B can be obtained by NORing the two outputs with an additional gate. A HIGH level on the
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F10166^
F10566^
F10166/F10566
F10166S
F10166
F10566
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F10162
Abstract: F10562 decoder active high outputs
Text: F10162 • F10562 l-OF-8 DECODER ACTIVE HIGH OUTPUTS D E S C R IP TIO N — T h e F10162 a n d F10562 a c c e p t a 3 -b it b in a r y in p u t a n d p ro v id e s e ig h t m u tu a lly e x c lu s iv e o u tp u ts . T h e s e le c te d o u tp u t w ill be H IG H w h ile a ll o th e r
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F10162
F10562
F10162
F10562
decoder active high outputs
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F10161
Abstract: No abstract text available
Text: F10161 • F10561 l-OF-8 DECODER ACTIVE LOW OUTPUTS DESCRIPTION — The F10161 and F10561 accept a 3-bit binary input and provides eight m utually exclusive outputs. The selected output w ill be LOW while all other outputs are HIGH. Two enable inputs force all outputs HIGH when either or both are
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F10161
F10561
F10161
F10561
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Untitled
Abstract: No abstract text available
Text: F10160 • F10560 12-BIT PARITY CHECKER/GENERATOR DESCRIPTION — The F10160 and F10560 are 12-Input Parity Generators. The output w ill be HIGH when an odd number of inputs are HIGH; typical delay is 4 ns. For applications requiring fewer than 12 inputs, unused inputs may be left open, since
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F10160
F10560
12-BIT
F10160
F10560
12-Input
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F10168
Abstract: F10568
Text: F101687» F 10568^ FIOK VOLTAGE COMPENSATED ECL QUAD LATCH/GATED OUTPUTS DESCRIPTION - The F10168 and F10568 contains four D type latches with a Common Enable Ec . When Ec is HIGH, outputs will follow the D inputs. Information is latched on the negative-going edge of Ec . Each latch output is combined with a separate gate control (Gn),
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F101687
F105687
F10168
F10568
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3bit to 8 Multiplexer
Abstract: VCC2-16 circuit diagram of 16-1 multiplexer F10164 F10564
Text: F10164 • F10564 8-INPUT MULTIPLEXER D E S C R IP TIO N — T h e F10164 a n d F10564 a c c e p t a 3 - b it a d d re s s a n d s e le c ts 1 -o f-8 LOGIC SYMBOL in p u ts . T h e e n a b le lin e , w h e n H IG H , fo rc e s th e o u tp u t L O W . T y p ic a l a d d re s s to o u tp u t
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F10164
F10564
F10164
F10564
Manuf12
3bit to 8 Multiplexer
VCC2-16
circuit diagram of 16-1 multiplexer
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Untitled
Abstract: No abstract text available
Text: F10565* F10165 8-INPUT PRIORITY ENCODER F10K VOLTAGE COMPENSATED ECL G E N E R A L DESCRIPTION - The F10165/F10565 are 8-Input Priority Encoders with output latches. The inputs are preassigned an order of priority, with D0 having the highest priority and D7 the lowest. Outputs Q2, CLi, Qo constitute a binary code identifying the highest order input
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F10565*
F10165
F10165/F10565
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Untitled
Abstract: No abstract text available
Text: S E M I C O N D U C T O R -n F1056 8-Bit S chottky B arrier Diode A rray General Description The ’ F1056 is an 8-bit Schottky barrier diode array designed to be employed as termination on the inputs to memory bus lines or CLOCK lines. This device is designed to suppress
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74F1056
F1056
74F1056SC
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Untitled
Abstract: No abstract text available
Text: F10164 • F10564 8-INPUT MULTIPLEXER D E S C R IP T IO N — The F10164 and F10564 a cce p t a 3 -b it address and selects 1-of-8 inpu ts. The enable line, w hen H IG H , fo rc e s the o u tp u t LOW. T yp ica l address to o u tp u t delays are 4 ns. LOGIC SYMBOL
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F10164
F10564
F10164
F10564
15X16)
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Untitled
Abstract: No abstract text available
Text: F10565* F10165 8-INPUT PRIORITY ENCODER F10K VOLTAGE COMPENSATED ECL GENERAL DESCRIPTION - The F10165/F10565 are 8 -Input Priority Encoders with output latches. The inputs are preassigned an order of priority, with D0 having the highest priority and D 7 the lowest. Outputs Q2, Q 1 , Q0 constitute a binary code identifying the highest order input
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F10565*
F10165
F10165/F10565
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l1113
Abstract: No abstract text available
Text: F 10168 • F 10568 F10K VOLTAGE COMPENSATED ECL QUAD LATCH/GATED OUTPUTS DESCRIPTION - The F10168 and F10568 contains four D type latches with a Common Enable Ec . When E c is HIGH, outputs will follow the D inputs. Information is latched on the negative-going edge of E c Each latch output is combined with a separate gate control (Gn),
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F10168
F10568
l1113
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Untitled
Abstract: No abstract text available
Text: F10162 • F10562 l-OF-8 DECODER ACTIVE HIGH OUTPUTS D E S C R IP TIO N — T h e F10162 a n d F 10562 a c c e p t a 3 - b it b in a ry in p u t a n d p ro v id e s e ig h t m u tu a lly e x c lu s iv e o u tp u ts . T h e s e le c te d o u tp u t w ill be H IG H w h ile a ll o th e r
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F10162
F10562
F10162
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Untitled
Abstract: No abstract text available
Text: F10168 « F 10568^ FIOK VOLTAGE COMPENSATED ECL QUAD LATCH/GATED OUTPUTS DESCRIPTION - The F10168 and F10568 contains four D type latches with a Common Enable Ec . When Ec is HIGH, outputs will follow the D inputs. Information is latched on the negative-going edge of Ec . Each latch output is combined with a separate gate control (Gn),
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F10168
F10168
F10568
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"Parity Checker"
Abstract: PIN DIAGRAM OF RJ50 10 pin F10160 F10560 RJ-50 RJ50
Text: F10160 • F10560 12-BIT PARITY C H EC K E R /G E N E R A TO R D E S C R IP T IO N — T h e F10160 a n d F10560 a re 1 2 - In p u t P a rity G e n e ra to rs . T h e o u tp u t w ill b e H IG H w h e n a n o d d n u m b e r o f in p u ts a re H IG H ; ty p ic a l d e la y is 4 ns. F o r
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F10160
F10560
12-BIT
F10160
F10560
12-lnput
12-INPUT
"Parity Checker"
PIN DIAGRAM OF RJ50 10 pin
RJ-50
RJ50
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F10161
Abstract: F10561
Text: F10161 • F10561 l-OF-8 DECODER ACTIVE LOW OUTPUTS D E S C R IP TIO N — T h e F10161 a n d F10561 a c c e p t a 3 - b it b in a r y in p u t a n d p ro v id e s e ig h t m u tu a lly e x c lu s iv e o u tp u ts . T h e s e le c te d o u tp u t w ill be L O W w h ile a ll o th e r
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F10161
F10561
F10161
F10561
11X13)
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fairchild ECL
Abstract: No abstract text available
Text: F10164 • F10564 8-INPUT MULTIPLEXER D E S C R IP T IO N — The F10164 and F10564 a c c e p t a 3 -b it address and selects 1-of-8 in p u ts. T h e e n able line, w hen H IG H , fo rc e s th e o u tp u t LOW , T yp ica l address to o u tp u t delays are 4 ns.
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F10164
F10564
F10164
F10564
fairchild ECL
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Untitled
Abstract: No abstract text available
Text: F10162 • F10562 l-OF-8 DECODER ACTIVE HIGH OUTPUTS D E S C R IP T IO N — T h e F 1 0 1 62 a n d F 1 0 5 62 a c c e p t a 3 - b it b in a r y in p u t a n d p ro v id e s e ig h t m u tu a lly e x c lu s iv e o u tp u ts . T h e s e le c te d o u t p u t w ill b e H IG H w h ile a ll o th e r
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F10162
F10562
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A1B11
Abstract: ecl f10k
Text: F10166^ F10566 5-BIT COMPARATOR F10K VOLTAGE COMPENSATED ECL DESCRIPTION - The F10166/F10566 are high-speed expandable 5-Bit Comparators for comparing the magnitude of two binary words. Two outputs are provided: A>B and A<B. A = B can be obtained by NORing the two outputs with an additional gate. A HIGH level on the
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F10166^
F10566
F10166/F10566
F10166S
A1B11
ecl f10k
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F10165
Abstract: F10565
Text: F 1 5 6 5 » F 1 1 6 5 ^ 8-INPUT PRIORITY ENCODER F10K VOLTAGE COMPENSATED ECL GENERAL DESCRIPTION - The F10165/F10565 are 8-Input Priority Encoders with output latches. The inputs are preassigned an order of priority, with D0 having the highest priority and
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F10565*
F10165
F10165/F10565
F10165
F10565
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Untitled
Abstract: No abstract text available
Text: F10166 • F10566 5-BIT COMPARATOR FIOK VOLTAGE COMPENSATED ECL DESCRIPTION - The F10166/F10566 are high-speed expandable 5-Bit Comparators or comparing the magnitude of two binary words. Two outputs are provided: A>B and A<B. A= B can be obtained by NORing the two outputs with an additional gate. A HIGH level on the
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F10166
F10566
F10166/F10566
F10166s
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Untitled
Abstract: No abstract text available
Text: F 1 0 1 6 0 • F 1 0 5 6 0 12-BIT PARITY CHECKER/GENERATOR D E S C R IP TIO N — The F10160 and F10560 are 1 2 -In p u t P arity G enerators. The o u tp u t w ill be H IG H w hen an odd nu m b e r o f in p u ts are H IG H ; ty p ic a l de la y is 4 ns. For
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12-BIT
F10160
F10560
12-INPUT
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Gunn Diode
Abstract: Microwave Silicon Detector Diode DW9248 microwave waveguide Marconi gunn Silicon Detector UHF diode varactor diode filter varactor
Text: Product List TYPE No. DESCRIPTION DA1304 DA1307 MILLIMETRE WAVE BALANCED MIXER 34.0 to 34.4GHz BALANCED MIXER C & X BAND DOUBLE BALANCED MIXER C & X BAND DOUBLE BALANCED MIXER X & J BAND DOUBLE BALANCED MIXER X & J BAND DOUBLE BALANCED MIXER X & J BAND DOUBLE BALANCED MIXER
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DA1304
DA1307
DA1321
DA1321-1
DA1338
DA1338-1
DA1338-2
DA1338-3
DA1349-2
DA1349-4
Gunn Diode
Microwave Silicon Detector Diode
DW9248
microwave waveguide
Marconi gunn
Silicon Detector
UHF diode
varactor diode filter
varactor
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