TNETA1545
Abstract: No abstract text available
Text: TNETA1545 DUAL DIFFERENTIAL PSEUDO-ECL TO ECL TRANSLATORS AND DUAL DIFFERENTIAL ECL TO PSEUDO-ECL TRANSLATORS SDNS005B – SEPTEMBER 1993 – REVISED OCTOBER 1995 D D D D D DW PACKAGE TOP VIEW Dual ECL to Pseudo-ECL and Pseudo-ECL to ECL Translators Single 5-V Power Supply
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TNETA1545
SDNS005B
24-Pin
TNETA1545
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CY101E383
Abstract: E383 R2170 ecl 84
Text: E383 CY101E383 ECL/TTL/ECL Translator and High-Speed Bus Driver Features • BiCMOS for optimum speed/power • High speed max. — 3.0 ns tPD TTL-to-ECL Functional Description The CY101E383 is a new-generation TTL-to-ECL and ECL-to-TTL logic level translator designed for high-perfor-
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CY101E383
CY101E383
8-A-00023
E383
R2170
ecl 84
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SG86A
Abstract: SG53A sg72a LVEP17 MC100ELxxx EP809 LVEL40 SLVS TR30 AND8020
Text: AN1568/D Interfacing Between LVDS and ECL Prepared by: Paul Lee Logic Applications Engineer ON Semiconductor http://onsemi.com APPLICATION NOTE ECL levels Today’s applications typically use ECL devices in the PECL mode. PECL Positive ECL is nothing more than
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AN1568/D
SG86A
SG53A
sg72a
LVEP17
MC100ELxxx
EP809
LVEL40
SLVS
TR30
AND8020
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CAN split termination
Abstract: SG86A SG53A AN1568
Text: AN1568/D Interfacing Between LVDS and ECL Prepared by: Paul Lee Logic Applications Engineer ON Semiconductor http://onsemi.com APPLICATION NOTE ECL levels Today’s applications typically use ECL devices in the PECL mode. PECL Positive ECL is nothing more than
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AN1568/D
r14525
AN1568/D
CAN split termination
SG86A
SG53A
AN1568
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Untitled
Abstract: No abstract text available
Text: SPST ECL Switches With Drivers 2662 Series V2.00 Features ● ● ● Broadband Frequency Ranges Environmentally Sealed ECL Compatible Description M/A-COM’s Emitter Coupled Logic ECL PIN diode switches offer multi-octave bands from UHF to Ku-band. Advantages of an ECL switch are narrow pulse width
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d2981
Abstract: CY101E383 E383 coaxial d8
Text: CY101E383 ECL/TTL/ECL Translator and HighĆSpeed Bus Driver Features D D tors. The part meets standard 100K logic BiCMOS for optimum speed/power The a newĆgeneration dent TTL ĆtoĆECL and ten independent Low skew < ± 1 ns ECL ĆtoĆTTL translators for ECL and TTL power/ground pins to reĆ
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CY101E383
CY101E383
d2981
E383
coaxial d8
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10H645
Abstract: E211 MC10E111 MPC973 AN1405
Text: AN1405/D ECL Clock Distribution Techniques Prepared by Todd Pearson ECL Applications Engineering http://onsemi.com APPLICATION NOTE This application note provides information on system design using ECL logic technologies for reducing system clock skew over
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AN1405/D
r14525
10H645
E211
MC10E111
MPC973
AN1405
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Hex schmitt trigger ecl
Abstract: 100325DMQB 5962-9153101MXA 5962-9153101MYA CERQUAD fmqb 100325J-QMLV 100325WFQMLV 5962-9153101VXA 5962
Text: National P/N 100325 - Low Power Hex ECL-to-TTL Translator Products > Military/Aerospace > Logic > ECL > 100325 100325 Product Folder Low Power Hex ECL-to-TTL Translator General Description Features Package & Models Datasheet Samples & Pricing Datasheet Title
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17-Aug-98
MN100325-X
5962-915res
16-Oct-2002]
ics/nat/100325
Hex schmitt trigger ecl
100325DMQB
5962-9153101MXA
5962-9153101MYA
CERQUAD
fmqb
100325J-QMLV
100325WFQMLV
5962-9153101VXA
5962
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EIA-644
Abstract: PECL-to-SN64LVDS33
Text: Interface Data Transmission Texas Instruments Incorporated The SN65LVDS33/34 as an ECL-to-LVTTL converter By Chris Sterzik Applications Specialist, Interface Products Introduction Figure 1. ECL characteristic load Emitter-coupled logic (ECL) has often been the physical
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SN65LVDS33/34
SLYT132
EIA-644
PECL-to-SN64LVDS33
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10H645
Abstract: AN1405 E211 MC10E111 MPC973
Text: AN1405 Application Note ECL Clock Distribution Techniques Prepared by Todd Pearson ECL Applications Engineering This application note provides information on system design using ECL logic technologies for reducing system clock skew over the alternative CMOS and TTL
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AN1405
BR1333
AN1405/D*
AN1405/D
10H645
AN1405
E211
MC10E111
MPC973
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Untitled
Abstract: No abstract text available
Text: TNETA1545 DUAL DIFFERENTIAL PSEUDO-ECL TO ECL TRANSLATORS AND DUAL DIFFERENTIAL ECL TO PSEUDO-ECL TRANSLATORS SDNS005B - SEPTEMBER 1993 - REVISED OCTOBER 1995 • Dual ECL to Pseudo-ECL and Pseudo-ECL to ECL Translators • Single 5-V Power Supply • Advanced BiCMOS Technology
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TNETA1545
SDNS005B
24-Pin
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b765
Abstract: PAL 008 PAL10016RD8 PAL1016RD8
Text: PRELIMINARY September 1986 ECL Registered and Latched Programmable Array Logic PAL Family General Description The registered and latched ECL PAL devices are the latest additions to National Semiconductor's ECL PAL family. The ECL PAL family utilizes National Semiconductor's advanced
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2-26A
AA32096
b765
PAL 008
PAL10016RD8
PAL1016RD8
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Untitled
Abstract: No abstract text available
Text: TIEPAL10016ET6C ECL-TO-TTLIMPACT-X" PAL TRANSLATOR CIRCUIT D3352, OCTOBER 1989 • ECL 100K Programmable Logic with ECL-to-TTL Translation JT PACKAGE TOP VIEW • ECL Control Inputs vcc[ '[ l[ l[ l[ l[ '[ '[ • 3-State TTL Outputs • IMPACT-X“ Process with Reliable
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TIEPAL10016ET6C
D3352,
300-mil
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TL 2272 R
Abstract: PAL1016RM4AJC
Text: ECL PAL10/10016RM4A r% \ ÆM National Semiconductor PAL10/10016RM4A ECL Registered Programmable Array Logic General Description The PAL10/10016RM4A is a member of the National Semi conductor ECL PAL family. The ECL PAL Series-A is char acterized by 4 ns maximum propagation delays combinato
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PAL10/10016RM4A
PAL10/10016RM4A
PAL1016RM4A/PAL10016RM4A
TL/L/9772-10
TL 2272 R
PAL1016RM4AJC
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Untitled
Abstract: No abstract text available
Text: ECL PAL10/10016RM4A m National ÆM Semiconductor PAL10/10016RM4A ECL Registered Programmable Array Logic General Description The PAL10/10016RM4A is a member of the National Semi conductor ECL PAL family. The ECL PAL Series-A is char acterized by 4 ns maximum propagation delays combinato
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PAL10/10016RM4A
PAL10/10016RM4A
PAL10/10016RM
Diagram--PAL1016RM4A/PAL10016RM4A
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Untitled
Abstract: No abstract text available
Text: TIEPAL10H16ET6C ECL-TO-TTLIMPACT-X PAL TRANSLATOR CIRCUIT D3283, OCTOBER 1989 JT P A C K A G E • ECL10KH Programmable Logic with ECL-to-TTL Translation ECL Control Inputs
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TIEPAL10H16ET6C
D3283,
ECL10KH
300-mil
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Untitled
Abstract: No abstract text available
Text: MC10H604 MC100H604 MOTOROLA Product Preview REGISTERED HEX TTL TO ECL TRANSLATOR Registered Hex TTL/ECL Translator The MC1 OH/100H604 is a 6-bit, registered, dual supply TTL to ECL translator. The de vice features differential ECL outputs as well as a choice between either a differential ECL
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MC10H604
MC100H604
OH/100H604
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Untitled
Abstract: No abstract text available
Text: ECL PAL10/10016P8 National Semiconductor PAL10/10016P8 ECL Programmable Array Logic General Description The PAL1016P8/10016P8 is the first member of an ECL programmable logic device family possessing common electrical characteristics, utilizing an easily accommodated
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PAL10/10016P8
PAL1016P8/10016P8
24-pin
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Untitled
Abstract: No abstract text available
Text: PAL10/10016P8 ECL Programmable Array Logic ECL PAL10/10016P8 National Semiconductor General Description The PAL1016PB/10016P8 is the first member of an ECL programmable logic device family possessing common electrical characteristics, utilizing an easily accommodated
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PAL10/10016P8
PAL10/10016P8
PAL1016PB/10016P8
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Untitled
Abstract: No abstract text available
Text: AN1405 Application Note ECL Clock Distribution Techniques Prepared by Todd Pearson ECL Applications Engineering This application note provides information on system design using ECL logic technologies for reducing system clock skew over the alternative CMOS and TTL
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AN1405
BR1333
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Untitled
Abstract: No abstract text available
Text: TYPES ECL2536, ECL2537 HLL-TO-ECL AND ICL-TO-HLL CONVERTERS ECL INTEGRATED CIRCUITS to H c< r "D I- m m ECL2500 SERIES EMITTER-COUPLED-LOGIC ECL LEVEL CONVERTERS FOR APPLICATION IN ULTRA-HIGH-SPEED D IG ITA L SYSTEMS O' description r* m ¿»2 The ECL2500 series is a compatible family of ECL functions
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ECL2536,
ECL2537
ECL2500
ECL2536
ECL2537
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Untitled
Abstract: No abstract text available
Text: ECL Surface-Mount Delay Modules ► 10k ECL logic levels. 10k ECL Programmable Delay Modules Part No. GECLPG301MX GECLPG302MX GECLPG303MX GECLPG304MX GECLPG305MX GEGLPG306MX GECLPG307MX GECLPG308MX GECLPG309MX GECLPG310MX Step Delay ns ± ns Max. Delay ns ± ns
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GECLPG301MX
GECLPG302MX
GECLPG303MX
GECLPG304MX
GECLPG305MX
GEGLPG306MX
GECLPG307MX
GECLPG308MX
GECLPG309MX
GECLPG310MX
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TTL Logic Family list
Abstract: No abstract text available
Text: PAL10/10016P8 ECL Programmable Array Logic ECL PAL10/10016P8 jg fl National Semiconductor General Description The PAL1016P8/10016P8 is the first member of an ECL programmable logic device family possessing common electrical characteristics, utilizing an easily accommodated
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PAL10/10016P8
PAL1016P8/10016P8
tl/l/6161-8
TTL Logic Family list
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AN-1405
Abstract: No abstract text available
Text: A N 1405 Application Note ECL Clock Distribution Techniques Prepared by Todd Pearson ECL Applications Engineering This application note provides information on system design using ECL logic technologies for reducing system clock skew over the alternative CMOS and TTL
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AN1405
BR1333
AN-1405
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