10H645
Abstract: AN1405 DL140 E211 MC10E111 MPC973
Text: AN1405 Application Note ECL Clock Distribution Techniques Prepared by Todd Pearson ECL Applications Engineering This application note provides information on system design using ECL logic technologies for reducing system clock skew over the alternative CMOS and TTL
|
Original
|
AN1405
DL140
AN1405/D*
AN1405/D
10H645
AN1405
E211
MC10E111
MPC973
|
PDF
|
Untitled
Abstract: No abstract text available
Text: Freescale Semiconductor, Inc. MOTOROLA Order Number: AN1405/D SEMICONDUCTOR TECHNICAL DATA Rev 1, 09/2001 AN1405 ECL Clock Distribution Techniques Prepared by: Todd Pearson ECL Applications Engineering Abstract This application note provides information on system design
|
Original
|
AN1405/D
AN1405
|
PDF
|
AN1091
Abstract: No abstract text available
Text: Freescale Semiconductor, Inc. Chapter Nine Application Notes Application Notes Freescale Semiconductor, Inc. Document Number Page AN1091/D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770 AN1405/D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777
|
Original
|
AN1091/D
AN1405/D
AN1406/D
AN1545/D
AN1934/D
AN1939/D
AN1091
|
PDF
|
Untitled
Abstract: No abstract text available
Text: Chapter Eight Application Notes Application Notes Document Number Page AN1091/D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644 AN1405/D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651 AN1406/D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
|
Original
|
AN1091/D
AN1405/D
AN1406/D
AN1545/D
AN1934/D
|
PDF
|
10H645
Abstract: AN1405 E211 MC10E111 MPC973
Text: AN1405 Application Note ECL Clock Distribution Techniques Prepared by Todd Pearson ECL Applications Engineering This application note provides information on system design using ECL logic technologies for reducing system clock skew over the alternative CMOS and TTL
|
Original
|
AN1405
BR1333
AN1405/D*
AN1405/D
10H645
AN1405
E211
MC10E111
MPC973
|
PDF
|
10H645
Abstract: E211 MC10E111 MPC973 AN1405
Text: AN1405/D ECL Clock Distribution Techniques Prepared by Todd Pearson ECL Applications Engineering http://onsemi.com APPLICATION NOTE This application note provides information on system design using ECL logic technologies for reducing system clock skew over
|
Original
|
AN1405/D
r14525
10H645
E211
MC10E111
MPC973
AN1405
|
PDF
|
Rosenberger
Abstract: ROSENBERGER* HSD ROSENBERGER hsd crystal generator 1GHz HSYNC, VSYNC Clock generator rgb Hsync Vsync generator Hsync Vsync RGB BNC connector led bnc to probe clips evb for LCD
Text: ISL34340, ISL34320 Evaluation Kit User Manual Application Note June 19, 2008 AN1405.0 Author: Peter Liu 1 Overview The ISL34340 evaluation kit enables the user to exercise the serdes in a lab environment and to see the high speed and parallel signals conveniently on an oscilloscope. The contents of the kit are shown
|
Original
|
ISL34340,
ISL34320
AN1405
ISL34340
com/data/EV/ISL34340
Rosenberger
ROSENBERGER* HSD
ROSENBERGER hsd
crystal generator 1GHz
HSYNC, VSYNC Clock generator rgb
Hsync Vsync generator
Hsync Vsync RGB
BNC connector led
bnc to probe clips
evb for LCD
|
PDF
|
MC10E111
Abstract: MPC973 10H645 AN1405 E211
Text: Freescale Semiconductor, Inc. MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order Number: AN1405/D Rev 1, 09/2001 ECL Clock Distribution Techniques AN1405 Prepared by: Todd Pearson ECL Applications Engineering Abstract This application note provides information on system design
|
Original
|
AN1405/D
AN1405
MC10E111
MPC973
10H645
AN1405
E211
|
PDF
|
Untitled
Abstract: No abstract text available
Text: Chapter Nine Application Notes Application Notes Document Number Page AN1091/D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770 AN1405/D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777 AN1406/D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783
|
Original
|
AN1091/D
AN1405/D
AN1406/D
AN1545/D
AN1934/D
AN1939/D
|
PDF
|
Untitled
Abstract: No abstract text available
Text: MOTOROLA Order Number: AN1405/D SEMICONDUCTOR TECHNICAL DATA Rev 1, 09/2001 AN1405 ECL Clock Distribution Techniques Prepared by: Todd Pearson ECL Applications Engineering Abstract This application note provides information on system design using ECL logic technologies for reducing system clock skew
|
Original
|
AN1405/D
AN1405
|
PDF
|
Untitled
Abstract: No abstract text available
Text: MOTOROLA Order Number: AN1405/D SEMICONDUCTOR TECHNICAL DATA Rev 1, 09/2001 AN1405 ECL Clock Distribution Techniques Prepared by: Todd Pearson ECL Applications Engineering Abstract This application note provides information on system design using ECL logic technologies for reducing system clock skew
|
Original
|
AN1405/D
AN1405
|
PDF
|
Untitled
Abstract: No abstract text available
Text: Freescale Semiconductor, Inc. Order number: AN1405 Rev 1, 09/2001 APPLICATION NOTE AN1405 ECL Clock Distribution Techniques By: Todd Pearson ECL Applications Engineering ABSTRACT This application note provides information on system design using ECL logic technologies for reducing system clock skew
|
Original
|
AN1405
|
PDF
|
100EL91
Abstract: MC100EL91 MC100EL91DW MC100EL91DWR2 MC100LVEL91
Text: MC100EL91 3.3V / 5VĄTriple LVPECL / PECL Input to -5V ECL Output Translator The MC100EL91 is a triple LVPECL / PECL input to ECL output translator. The device receives standard or low voltage differential PECL signals, determined by the VCC supply level, and translates them
|
Original
|
MC100EL91
MC100EL91
MC100LVEL91.
r14525
MC100EL91/D
100EL91
MC100EL91DW
MC100EL91DWR2
MC100LVEL91
|
PDF
|
E212 transistor
Abstract: E112 E212 MC100E112 MC100E112FN MC10E112 MC10E112FN MC10E112FNR2 D200-400
Text: MC10E112, MC100E112 5VĄECL Quad Driver The MC10E/100E112 is a quad driver with two pairs of OR/NOR outputs from each gate, and a common, buffered enable input. Using the data inputs the device can serve as an ECL memory address fan-out driver. Using just the enable input, the device serves as a clock
|
Original
|
MC10E112,
MC100E112
MC10E/100E112
MC10E/100E111
r14525
MC10E112/D
E212 transistor
E112
E212
MC100E112
MC100E112FN
MC10E112
MC10E112FN
MC10E112FNR2
D200-400
|
PDF
|
|
|
KPT25
Abstract: EPT25 MC100EPT25 MC100EPT25D MC100EPT25DR2 MC100EPT25DT MC100EPT25DTR2 KA25 kpt25 alyw
Text: MC100EPT25 −3.3V / −5V Differential ECL to +3.3V LVTTL Translator The MC100EPT25 is a Differential ECL to LVTTL translator. This device requires +3.3 V, -3.3 V to -5.2 V, and ground. The small outline 8-lead package and the single gate of the EPT25 make it ideal
|
Original
|
MC100EPT25
MC100EPT25
EPT25
r14525
MC100EPT25/D
KPT25
MC100EPT25D
MC100EPT25DR2
MC100EPT25DT
MC100EPT25DTR2
KA25
kpt25 alyw
|
PDF
|
LQFP32
Abstract: LQFP-32 MC100 MC100EPT622 MC100EPT622FA MC100EPT622FAR2
Text: MC100EPT622 3.3V LVTTL/LVCMOS to LVPECL Translator The MC100EPT622 is a 10- Bit LVTTL/LVCMOS to LVPECL translator. Because LVPECL Positive ECL levels are used only +3.3 V and ground are required. The device has an OR- ed enable input which can accept either LVPECL (ENPECL) or TTL/LVCMOS inputs
|
Original
|
MC100EPT622
MC100EPT622
MC100
EPT622
LQFP-32
r14525
MC100EPT622/D
LQFP32
LQFP-32
MC100
MC100EPT622FA
MC100EPT622FAR2
|
PDF
|
marking CODE D2B
Abstract: MC100E104 MC100E104FN MC100E104FNR2 MC10E104 MC10E104FN MC10E104FNR2 marking D3B ECL IC NAND
Text: MC10E104, MC100E104 5VĄECL Quint 2ĆInput AND/NAND Gate The MC10E/100E104 is a quint 2-input AND/NAND gate. The function output F is the OR of all five AND gate outputs, while F is the NOR. The Q outputs need not be terminated if only the F outputs are to be
|
Original
|
MC10E104,
MC100E104
MC10E/100E104
MC10E104FN
EIA/JESD78
r14525
MC10E104/D
marking CODE D2B
MC100E104
MC100E104FN
MC100E104FNR2
MC10E104
MC10E104FN
MC10E104FNR2
marking D3B
ECL IC NAND
|
PDF
|
KVT23
Abstract: MC100LVELT23 MC100LVELT23D MC100LVELT23DR2 MC100LVELT23DT
Text: MC100LVELT23 3.3V Dual Differential LVPECL to LVTTL Translator The MC100LVELT23 is a dual differential LVPECL to LVTTL translator. Because LVPECL Positive ECL levels are used only +3.3 V and ground are required. The small outline 8-lead package and the dual gate design of the LVELT23 makes it ideal for applications which
|
Original
|
MC100LVELT23
MC100LVELT23
LVELT23
MC100LVELT23/D
KVT23
MC100LVELT23D
MC100LVELT23DR2
MC100LVELT23DT
|
PDF
|
MC100EP90
Abstract: MC100EP90DT MC100EP90DTR2 MC10EP90 MC10EP90DT MC10EP90DTR2
Text: MC10EP90, MC100EP90 -3.3V / -5VĄTriple ECL Input to LVPECL/PECL Output Translator The MC10/100EP90 is a TRIPLE ECL TO LVPECL/PECL translator. The device receives differential LVECL or ECL signals and translates them to differential LVPECL or PECL output signals.
|
Original
|
MC10EP90,
MC100EP90
MC10/100EP90
r14525
MC10EP90/D
MC100EP90
MC100EP90DT
MC100EP90DTR2
MC10EP90
MC10EP90DT
MC10EP90DTR2
|
PDF
|
MC100E116
Abstract: MC100E116FN MC100E116FNR2 MC10E116 MC10E116FN MC10E116FNR2 E116
Text: MC10E116, MC100E116 5VĄECL Quint Differential Line Receiver The MC10E/100E116 is a quint differential line receiver with emitter-follower outputs. For applications which require bandwidths greater than that of the E116, the E416 device may be of interest.
|
Original
|
MC10E116,
MC100E116
MC10E/100E116
r14525
MC10E116/D
MC100E116
MC100E116FN
MC100E116FNR2
MC10E116
MC10E116FN
MC10E116FNR2
E116
|
PDF
|
MC100LVEL01
Abstract: MC100LVEL01D 1085 SPICE model
Text: MC100LVEL01 3.3VĄECL 4-Input OR/NOR The MC100LVEL01 is a 4–input OR/NOR gate. The device is functionally equivalent to the EL01 device and works from a 3.3 V supply. With AC performance similar to the EL01 device, the LVEL01 is ideal for low voltage applications which require the ultimate in
|
Original
|
MC100LVEL01
MC100LVEL01
LVEL01
KVL01
r14525
MC100LVEL01/D
MC100LVEL01D
1085 SPICE model
|
PDF
|
KEL04
Abstract: HL04 HEL04 e104 MC100EL04 MC10EL04 HL-04
Text: MC10EL04, MC100EL04 5VĄECL 2ĆInput AND/NAND The MC10EL/100EL04 is a 2-input AND/NAND gate. The device is functionally equivalent to the E104 device with higher performance capabilities. With propagation delays and output transition times significantly faster than the E104, the EL04 is ideally suited for those
|
Original
|
MC10EL04,
MC100EL04
MC10EL/100EL04
AND8003/D
r14525
MC10EL04/D
KEL04
HL04
HEL04
e104
MC100EL04
MC10EL04
HL-04
|
PDF
|
N100
Abstract: NB100LVEP17 NB100LVEP17DT NB100LVEP17DTR2 NB100LVEP17MN TSSOP-20 qfn24 socket N100 transistor QFN-24
Text: NB100LVEP17 2.5V / 3.3V / 5V ECL Quad Differential Driver/Receiver The NB100LVEP17 is a 4-bit differential line receiver. The design incorporates two stages of gain, internal to the device, making it an excellent choice for use in high bandwidth amplifier applications.
|
Original
|
NB100LVEP17
NB100LVEP17
r14525
NB100LVEP17/D
N100
NB100LVEP17DT
NB100LVEP17DTR2
NB100LVEP17MN
TSSOP-20
qfn24 socket
N100 transistor
QFN-24
|
PDF
|
Untitled
Abstract: No abstract text available
Text: AN1405 Application Note ECL Clock Distribution Techniques Prepared by Todd Pearson ECL Applications Engineering This application note provides information on system design using ECL logic technologies for reducing system clock skew over the alternative CMOS and TTL
|
OCR Scan
|
AN1405
BR1333
|
PDF
|
