VDS1120
Abstract: VDS2110 VDS5010 VDS3110 ECL10KH VDS1110 VDS2120 VDS5020 ECL10K 0-30ns
Text: Variable Delay Lines VDS Ultra High-Speed Variable Delay Lines The VDS family of high-speed vailable delay lines is available in a dual in-line package for a variety of types in either standard or custom specifications. FEATURES • High-speed SMD delay lines that have achieved 40 step
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84001A/08
VDS1120
VDS2110
VDS5010
VDS3110
ECL10KH
VDS1110
VDS2120
VDS5020
ECL10K
0-30ns
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micro servo 9g
Abstract: uPa2003 micro servo 9g tower pro 2SK1060 uPD3599 201 Zener diode 2SK2396 upc1237 infrared sensor TSOP - 1836 2SK518
Text: The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call
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V20HL,
V25HS,
V30HL,
V30MX,
V35HS,
V40HL,
V50HL,
V55PI,
X10679EJDV0SG00
micro servo 9g
uPa2003
micro servo 9g tower pro
2SK1060
uPD3599
201 Zener diode
2SK2396
upc1237
infrared sensor TSOP - 1836
2SK518
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K1149
Abstract: 50-to-75 RASCO k1519 ECL10KH K1149BA K1149CA K1523BA K1524AA power supply 5v dc
Text: K1149 Series ECL Compatible Oscillators ECL10KH Based Design - provides im proved rise and fall times, duty cycle, noise margins and power supply rejection over the earlier 10K family while retaining compatibil ity. Open emitter output allows the user to
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K1149
ECL10KH
K1149BA,
K1149CA
50-to-75
RASCO
k1519
K1149BA
K1149CA
K1523BA
K1524AA
power supply 5v dc
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Untitled
Abstract: No abstract text available
Text: ECL10KH for High Performance System Design The designer of high-perform ancedigital system s now has new alternatives with the introduction o f M onolithic M em ories’ E C L 10KH fam ily of Logic. M onolithic Mem ories’ E C L 10KH devices are com pletely equivalent to M otorola’s M E C L 10KH. This
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ECL10KH
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Untitled
Abstract: No abstract text available
Text: ECL10KH High-Speed Emitter-Coupled Logic Family MC10H101 Quad OR/NOR Gate Features/ Benefits Ordering Inform ation • Propagation delay, 1 ns typical PART NUMBER • Power dissipation 25 mW/gate MC10H101 • Noise margin 150 mV PACKAGE TEMPERATURE { J,N,NL 20
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ECL10KH
MC10H101
10K-compatible.
MC10H101
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MC10H101
Abstract: ECL10KH
Text: ECL10KH High-Speed Em itter-Coupled Logic Fam ily M C10H101 Quad O R/NO R Gate Ordering Inform ation Features/B enefits • Propagation delay, 1 ns typical PART NUMBER • Power dissipation 25 mW/gate MC10H101 PACKAGE TEMPERATURE J,N,NL 20 Com • Noise margin 150 mV
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ECL10KH
MC10H101
10K-compatlble.
MC10H101
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Untitled
Abstract: No abstract text available
Text: ECL10KH * V l ' n Hiah-Soeed • »» »■ ■ » I 1« « Em itter-Coupled Logic Fam ily 1 1 /^ 4 A lw i\# ■ U 4 - I PRELIMINARY | in f o r m a t io n A 4 This docum ent contains spe! cifications and inform ation ■ Quad OR/NOR Gate
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ECL10KH
MC10H101
TheMC10H101
50-ohm
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quad 3 input or gate
Abstract: ECL10KH MC10H131
Text: Table of Contents ECL10KH Contents for Section 13 . 13-2 Selection Guide for ECL10KH . 13-2 ECL10KH for High Performance System Design . 13-3 MC10H101 Quad OR/NOR Gate . 13-4
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ECL10KH
ECL10KH
MC10H101
MC10H103
MC10H102
MC10H105
MC1QH104
MC10H107
MC10H109
quad 3 input or gate
MC10H131
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Untitled
Abstract: No abstract text available
Text: TIEPAL10H16ET6C ECL-TO-TTLIMPACT-X PAL TRANSLATOR CIRCUIT D3283, OCTOBER 1989 JT P A C K A G E • ECL10KH Programmable Logic with ECL-to-TTL Translation ECL Control Inputs
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TIEPAL10H16ET6C
D3283,
ECL10KH
300-mil
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Untitled
Abstract: No abstract text available
Text: Digitally Programmable Dclsy Units SER|ES:PDU-1064H * 6-Bit E C L Interfaced Features: • ■ ■ ■ ■ ■ Low propagation delay Input & output ECL buffered 6-B IT ECL program m able delay line Output sam e polarity of input Com pletely interfaced C om pact & low profile
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PDU-1064H
PDU-1064H-6
PDU-1064H-8
PDU-1064H-10
PDU-1064H-3
PDU-1064H-4
PDU-1064H-5
PDU-1064H-0
PDU-1064H-1
PDU-1064H-2
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Untitled
Abstract: No abstract text available
Text: 2-Phase Gated-Delay Line Oscillator SERIES: 16 pins DIP ECL Interfaced DLO-50 data delay p devices; m e . Features: • Continuous or keyable wavetrain. ■ Locked synchronization achieved with random gating signal. ■ Low profile module. ■ Available from 50 MHZ to 100 MHZ
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DLO-50
ECL-10KH
DLO-50-50
DLO-SO-55
DLO-50-60
DLO-50-65
DLO-50-70
DLO-50-75
DLO-50-80
DLO-50-85
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H158
Abstract: ECL10KH MC10H158 FW00
Text: ECL 10KH High-Speed Emitter-Coupled Logic Family MC10H158 QUAD 2-Input Multiplexer p r e l im in a r y ' in f o r m a t io n T h is d o c u m e n t contains, spec ific a tio n s and in fo rm a tio n | w h ic h are subject, to cha n g e . I Ordering Information
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MC10H158
10K-Compatible
MC10H158
500linear
H158
ECL10KH
FW00
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memorias
Abstract: ECL10KH MC10H106
Text: EC L10K H High Speed Em itter Coupled Logic Fam ily M C 10H 106 IH p le 4 -3 -3 Input NOR Gate Features/ Benefits Ordering Inform ation • Propagation delay, 1 ns typical PART NUMBER PACKAGE MC10H106 J, N, NL TEMPERATURE • 36 mW typical/gate no load • Noise margin 150 mV
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ECL10KH
MC10H106
10K-compatlble
MC10H106
M10H106
50-il
memorias
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ECL10KH
Abstract: MC10H130 MC10H131
Text: ECL 10KH High-Speed Em itter-Coupled Logic Fam ily Dual Latch M C 10H 130 F eatures/ Benefits O rdering Inform ation • Propagation delay, 1 ns typical PART NUMBER PACKAGE TEMPERATURE MC10H130 J,N,NL 20 Com • Power dissipation, 155 mW typical • Noise margin 150 mV
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MC10H130
10K-compatible
MC10H130
ECL10KH
MC10H131
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ecl10kh
Abstract: MC10H209
Text: E C L 1 0 K H High Speed Em itter Coupled Logic Fam ily M C 10H 209 Dual 4-5 Input OR/NOR Gate Features/Benefits • Propagation delay, 0.75 ns typical Ordering Information PART NUMBER PACKAGE TEMPERATURE M C10H209 J,N ,IMI- Com • 125 mW typical no load
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ECL10KH
MC10H209
10K-compatlble
MC10H209
50-il
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PWC-11-10
Abstract: PWC-11-15 PWC-11-20 PWC-11-25 PWC-11-6 PWC-11-7 PWC-11-8 PWC-11-9
Text: Pulse Width Controller SERIES: ECL Interfaced 16 pins DIP PWC-11 data VM/ delay ^O/ devicesYinc. Features: • ■ ■ ■ ■ Exact control of pulse width Rising edge trigger Auto-insertable ECL input & outputs High speed * r '$ E , Specifications: ■ ■
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PWC-11
ECL-10KH
PWC-11
PWC-11-20
PWC-11-25
PWC-11-30
PWC-11-35
PWC-11-40
PWC-11-45
PWC-11-50
PWC-11-10
PWC-11-15
PWC-11-6
PWC-11-7
PWC-11-8
PWC-11-9
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ECL10KH
Abstract: MC10H103
Text: ECL 1 0K H H igh-Speed E m itter-C oupled Logic Fam ily M C 10H 103 Quad 2 -In p u t OR G ate O rd e rin g Inform ation F e a tu re s / B e n e fits • Propagation delay, 1.0 ns typical PART NUMBER • Power dissipation 25 mW/gate MC10H103 • Noise margin 150 mV
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MC10H103
ECL10KH
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C10H210
Abstract: No abstract text available
Text: D T j b 3 D3 4 1 0 O O O b l ö i MONOLITHIC MEMORIES IN C fll E C L 10 KH High-Speed Emitter-Coupled Logic Fam ily M C 10H 210/M C 10H 211 3-Input, 3-Output O R /N O R Gates Features/Benefits °r T -4 3 -2 1 Ordering Information • Propagation delay, 1.0 ns typical
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210/M
10K-compatlble
MC10H210
MC10H211
MC10H211
C10H210
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quad 4 to 1 mux
Abstract: No abstract text available
Text: ECL 10KH High-Speed Emitter-Coupled Logic Family M C 10H 174 D ual4-to-1 M ultiplexer Features/ Benefits Ordering Information • Propagation delay 1.5 ns typical I PART NUMBER PACKAGE TEMPERATURE j J,N,NL 20 Com • Power dissipation, 305 mW typical • Noise margin 150 mV
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MC10H174
MC10H174
quad 4 to 1 mux
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max2923
Abstract: ecl 10K
Text: ECL 10KH High-Speed Emitter-Coupled Logic Family MC1 OH 102/Q uad 2-Input NOR Gate M C 10H 105/Triple 2 -3 -2 Input OR/NOR Gate Ordering Inform ation Features/B enefits • Propagation delay, 1 ns typical PART NUMBER • Power dissipation 25 mW/gate PACKAGE
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102/Q
105/Triple
MC10H105
MC10H102
MC10H105
MC10H102
max2923
ecl 10K
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C10H159
Abstract: No abstract text available
Text: I PRELIMINARY INFORMATION E C L 10KH High-Speed Emitter-Coupled Logic Family M C10H159 Quad 2-Input Inverting Multiplexer with Enable This docum ent contains spe cifications and inform ation which are subject to change. Features/Benefits Ordering Information
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C10H159
10K-compatlble
MC10H159
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d3177
Abstract: No abstract text available
Text: EC L 10KH High-Speed Emitter-Coupled Logic Family M C 10H 173 QUAD 2-Input Multiplexer With Latch Features/Benefits PRELIMINARY INFORMATION T h is d o c u m e n t c o n ta in s s p e c ific a tio n s a n d in fo rm a tio n w h ic h a re s u b je c t to c h a n g e .
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MC10H173
10K-compatible
d3177
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Untitled
Abstract: No abstract text available
Text: data W3V/ delay W devices/inc. Digital Delay Units SERIES DDU-12H 10 Taps ECL Interfaced Test Conditions: inp u t p u ls e -w id th : 1 5 0 % o f to tal d elay. In p u t pulse rise -tim e: « 6 ns. In p u t p ulse vo ltag e: ,7V Features: • Input & Output ECL Buffered
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DDU-12H
ECL-10KH
DDU-12H-10
DDU-12H-20
DDU-12H-25
DDU-12H-40
DDU-12H-50
DDU-12H-75
DDU-12H-100
DDU-12H-150
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Untitled
Abstract: No abstract text available
Text: Digitally Programmable Delay Units S ER IES : PDU-10256H 8-Bit E C L Interfaced Test Conditions Specifications: • In p u t p u ls e -w id th : ■ Delay variation: Monotonic in one direction. ■ Programmed delay tolerance: ± 5% or 2 ns whichever is greater.
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PDU-10256H
ECL-10KH
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