DESIGNWARE Search Results

DESIGNWARE Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
CY3146 Abstract: features of verilog 1995 Warp Cypress Hewlett Packard Text: 46 CY3146 Cypress Synopsys Bolt-in Kit Features System Requirements • Seamless integration with your Synopsys Design Compiler and FPGA Compiler tools • Powerful VHDL or Verilog design entry • DesignWare library support • Supports the FLASH370i™ family of CPLDs	Original	CY3146 FLASH370iTM CY3146 FLASH370i, features of verilog 1995 Warp Cypress Hewlett Packard	PDF
DesignWare Abstract: IEEE1076 Text: High-Level Design Resources Vendor Libraries Actel provides support for synthesis and simulation products offered by leading EDA vendors. Synthesis technology libraries are available for Synospys FPGA Compiler, including library support for Synospys DesignWare and Synopsys VSS	Original		PDF
quicklogic Abstract: DesignWare Text: Interface Kit HIGHLIGHTS Supports both VHDL and Verilog HDL standards — enabling a complete high-level design methodology. Supports DesignWare for optimal area and speed implementations of adders and counters. Supports synthesis with Design Compiler or FPGA Compiler.	Original		PDF
and or Abstract: CY3146 Text: fax id: 6258 1CY 314 6 CY3146 Cypress Synopsys Bolt-in Kit Features System Requirements • Seamless integration with your Synopsys Design Compiler and FPGA Compiler tools • Powerful VHDL or Verilog design entry • DesignWare library support • Supports the FLASH370i™ family of CPLDs	Original	CY3146 FLASH370iTM CY3146 FLASH370i, and or	PDF
DesignWare Abstract: synopsys QUICKLOGIC Text: Interface Kit HIGHLIGHTS Supports both VHDL and Verilog HDL standards — enabling a complete high-level design methodology. Supports DesignWare for optimal area and speed implementations of adders and counters. Supports synthesis with Design Compiler or FPGA Compiler.	Original		PDF
GCM 38112 Abstract: Wifi to I2C ST ATUC3A4256S AT32UC3A3 dsp ssb modulation demodulation barcode reader using avr AT32UC3A64 ATUC3A3256 DesignWare Hi-Speed USB On-The-Go Controller AT32UC3A3256S Text: Features • High Performance, Low Power 32-bit AVR Microcontroller • • • • • • • • • • • • – Compact Single-Cycle RISC Instruction Set Including DSP Instruction Set – Read-Modify-Write Instructions and Atomic Bit Manipulation	Original	32-bit 51DMIPS/MHz 92DMIPS 66MHz 36MHz 256KBytes, 128KBytes, 64KBytes 32072D04/2011 GCM 38112 Wifi to I2C ST ATUC3A4256S AT32UC3A3 dsp ssb modulation demodulation barcode reader using avr AT32UC3A64 ATUC3A3256 DesignWare Hi-Speed USB On-The-Go Controller AT32UC3A3256S	PDF
BGA144 13x13 package Abstract: DesignWare Hi-Speed USB On-The-Go Controller SCR trickle charger circuit trickle battery charger circuit using scr 7476 up down counter Palmchip designware usb otg IHI-0011A M25PXX hitachi elko Text: AS3525-A/-B C22O22 Data Sheet, Confidential å Datasheet, Confidential AS3525 Advanced Audio Processor System 1 Description This highly flexible and fully integrated audio processor system AS3525 combines strong calculating power, high performance audio features with system power management options for battery	Original	AS3525-A/-B C22O22 AS3525 AS3525) 32-Bit 200MIPS BGA144 13x13 package DesignWare Hi-Speed USB On-The-Go Controller SCR trickle charger circuit trickle battery charger circuit using scr 7476 up down counter Palmchip designware usb otg IHI-0011A M25PXX hitachi elko	PDF
EP20K1000C Abstract: EP20K200C EP20K400C EP20K600C EPC16 FA12 ep20k apex board Text: APEX 20KC Programmable Logic Device February 2002 ver. 2.0 Features. Data Sheet • ■ Programmable logic device PLD manufactured using a 0.15-µm alllayer copper-metal fabrication process – 25 to 35% faster design performance than APEXTM 20KE devices	Original		PDF
Sony IMX 183 Abstract: Sony sony cmos sensor imx 178 Sony imx 214 Sony ImX 252 sony cmos sensor imx 226 Sony IMX 219 CMOS Sony "IMX 219" CMOS sony IMX 322 cmos sony cmos sensor imx 185 Text: i.MX 6Solo/6DualLite Applications Processor Reference Manual Document Number: IMX6SDLRM Rev. 1, 04/2013 i.MX 6Solo/6DualLite Applications Processor Reference Manual, Rev. 1, 04/2013 2 Freescale Semiconductor, Inc. Contents Section number Title Page Chapter 1	Original		PDF
design fir filter tin verilog Abstract: EPC1441 EPF6010A EPF6016 EPF6016A EPF6024A 74MIN FLEX 6000 family Text: FLEX 6000 Programmable Logic Device Family November 1999, ver. 4.02 Features. Data Sheet • ■ ■ Provides an ideal low-cost, programmable alternative to highvolume gate array applications and allows fast design changes during prototyping or design testing	Original	96-mil EPF6010A EPF6016A 100-pin EPF6010A, EPF6016A, EPF6024A 256-pin design fir filter tin verilog EPC1441 EPF6016 74MIN FLEX 6000 family	PDF
EPF10K100B Abstract: EPF10K100E EPF10K130E EPF10K200E EPF10K30E EPF10K50E EPF10K50S Text: FLEX 10KE Embedded Programmable Logic Devices March 2001, ver. 2.3 Data Sheet • Features. ■ ■ f Embedded programmable logic devices PLDs , providing system-on-a-programmable-chip (SOPC) integration in a single device – Enhanced embedded array for implementing megafunctions	Original	16-bit EPF10K100B EPF10K100E EPF10K130E EPF10K200E EPF10K30E EPF10K50E EPF10K50S	PDF
EPF10K50S Abstract: EPF10K100B EPF10K100E EPF10K130E EPF10K200E EPF10K30E EPF10K50E FLEX controller vhdl code Text: FLEX 10KE Embedded Programmable Logic Family September 2000, ver. 2.10 Features. Data Sheet • ■ ■ f Embedded programmable logic devices PLDs , providing system-on-a-programmable-chip integration in a single device – Enhanced embedded array for implementing megafunctions	Original	16-bit EPF10K50S EPF10K100B EPF10K100E EPF10K130E EPF10K200E EPF10K30E EPF10K50E FLEX controller vhdl code	PDF
XC4000X Abstract: XC9500 schematic diagram AND gates Text: R ALLIANCE Series Software Synopsys FPGA Compiler Implementation Flow Module Generators EDN 3rd Party Schematic Simulator May require user defined symbol if not part of a Xilinx provided interface. .V .VHD LogiBLOX .NGC= Xilinx Binary Netlist VHDL Verilog	Original		PDF
programmable multi pulse waveform generator cpld Abstract: cb8cle synopsys Platform Architect DataSheet XC2064 XC3090 XC4005 XC5210 XC9000 XC9500 XC9500XL Text: CPLD Synthesis Design Guide Getting Started with Synopsys for CPLDs Designing with CPLDs Compiling and Fitting a CPLD Design Simulating your Design Library Component Specifications Attributes Fitter Command and Option Summary CPLD Synthesis Design Guide Printed in U.S.A.	Original	XC2064, XC3090, XC4005, XC5210, XC-DS501 programmable multi pulse waveform generator cpld cb8cle synopsys Platform Architect DataSheet XC2064 XC3090 XC4005 XC5210 XC9000 XC9500 XC9500XL	PDF

ahb arbiter in mentor Abstract: 16x16x1.4 Text: GS40 0.11-µm CMOS Standard Cell/Gate Array Version 0.5 May 19, 2000 Copyright  Texas Instruments Incorporated, 2000 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the	Original		PDF
verilog code voltage regulator Abstract: verilog code for 32 bit risc processor vhdl code for watchdog timer of ATM fastscan verilog code for 16 bit risc processor NET 1672 analog to digital converter verilog Multi-Channel DMA Controller verilog code arm processor Texas Instruments I2C Text: GS30TR 0.15-µm CMOS Standard Cell/Gate Array Version 1.2 May 17, 2000 Copyright  Texas Instruments Incorporated, 2000 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the	Original	GS30TR verilog code voltage regulator verilog code for 32 bit risc processor vhdl code for watchdog timer of ATM fastscan verilog code for 16 bit risc processor NET 1672 analog to digital converter verilog Multi-Channel DMA Controller verilog code arm processor Texas Instruments I2C	PDF
EP1K10 Abstract: EP1K100 EP1K30 EP1K50 EPC1441 EPC16 JESD-71 Text: ACEX 1K Programmable Logic Device Family May 2003, ver. 3.4 Features. Data Sheet • ■ ■ ■ Table 1. ACEXTM 1K Device Features Feature EP1K10 EP1K30 EP1K50 EP1K100 Typical gates 10,000 30,000 50,000 100,000 Maximum system gates 56,000 119,000 199,000	Original	EP1K10 EP1K30 EP1K50 EP1K100 EP1K10 EP1K100 EP1K30 EP1K50 EPC1441 EPC16 JESD-71	PDF
design fir filter tin verilog Abstract: EPC1441 EPF6010A EPF6016 EPF6016A EPF6024A altera TTL library orcad pcb footprint Text: FLEX 6000 Programmable Logic Device Family March 2001, ver. 4.1 Features. Data Sheet • ■ ■ Provides an ideal low-cost, programmable alternative to highvolume gate array applications and allows fast design changes during prototyping or design testing	Original		PDF
circuit diagram of 8-1 multiplexer design logic Abstract: vhdl code for phase frequency detector for FPGA verilog code for distributed arithmetic VERILOG Digitally Controlled Oscillator Signal Path Designer Text: Xilinx Design Reuse Methodology for ASIC and FPGA Designers SYSTEM-ON-A-CHIP DESIGNS REUSE SOLUTIONS Xilinx An Addendum to the: REUSE METHODOLOGY MANUAL FOR SYSTEM-ON-A-CHIP DESIGNS 2 Table of Contents 1 Introduction . 3	Original		PDF
C9715 Abstract: ti f32 EPF10K10 EPF10K10A EPF10K20 EPF10K30 EPF10K30A EPF10K40 EPF10K50 EPF10K100-1 Text: FLEX 10K Embedded Programmable Logic Family Data Sheet FLEX 10K エンベデッド・プログラマブル・ロジック・ファミリ 1998年 1 月 ver.3 特長 Data Sheet • ■ ■ シングル・デバイス内にシステム機能が集積化できる業界初のエンベ	Original	960RAM 048RAM 1-1990JTAG EPF10K10 EPF10K10A EPF10K20 EPF10K30 EPF10K30A EPF10K30B EPF10K40 C9715 ti f32 EPF10K10 EPF10K10A EPF10K20 EPF10K30 EPF10K30A EPF10K40 EPF10K50 EPF10K100-1	PDF
EP20K100E Abstract: EP20K160E EP20K200 EP20K200E EP20K300E EP20K30E EP20K400 EP20K400E EP20K60E EP20K100 Text: APEX 20K Programmable Logic Device Family August 2001, ver. 4.0 Features. Data Sheet • ■ Industry’s first programmable logic device PLD incorporating system-on-a-programmable-chip (SOPC) integration – MultiCoreTM architecture integrating look-up table (LUT) logic,	Original		PDF
Untitled Abstract: No abstract text available Text: Features • High Performance, Low Power 32-bit AVR Microcontroller • • • • • • • • • • • • – Compact Single-Cycle RISC Instruction Set Including DSP Instruction Set – Read-Modify-Write Instructions and Atomic Bit Manipulation	Original	32-bit 51DMIPS/MHz 92DMIPS 66MHz 36MHz 32072G11/2011	PDF
Untitled Abstract: No abstract text available Text: FLEX 8000 Programmable Logic Device Family May 1999, ver. 10 Features. D a ta she et • ■ ■ ■ ■ Low-cost, high-density, register-rich CMOS programmable logic device PLD family (see Table 1) 2,500 to 16,000 usable gates 282 to 1,500 registers System-level features	OCR Scan	EPF8452A EPF8636GC192 EPF8636A EPF8820A EPF81500A	PDF
Untitled Abstract: No abstract text available Text: Introduction May 1999, ver. 6 Overview Designers today are challenged with producing quality products in a faster time frame and at lower costs than ever before. Altera offers a complete solution to help designers meet their customers' demands. Altera's System-on-a-Programmable-Chip solution combines	OCR Scan		PDF

Privacy Settings

DESIGNWARE Search Results

DESIGNWARE Datasheets Context Search

CY3146

DesignWare

quicklogic

and or

DesignWare

GCM 38112

BGA144 13x13 package

EP20K1000C

Sony IMX 183

design fir filter tin verilog

EPF10K100B

EPF10K50S

XC4000X

programmable multi pulse waveform generator cpld

ahb arbiter in mentor

verilog code voltage regulator

EP1K10

design fir filter tin verilog

circuit diagram of 8-1 multiplexer design logic

C9715

EP20K100E

Untitled

Untitled

Untitled