CY7C1916BV18 Search Results

CY7C1916BV18 Datasheets (5)

Part	ECAD Model	Manufacturer	Description	Curated	Type	PDF
CY7C1916BV18		Cypress Semiconductor	18-Mbit DDR-II SRAM 2-Word Burst Architecture		Original	PDF
CY7C1916BV18-167BZC		Cypress Semiconductor	18-Mbit DDR-II SRAM 2-Word Burst Architecture		Original	PDF
CY7C1916BV18-167BZXC		Cypress Semiconductor	18-Mbit DDR-II S		Original	PDF
CY7C1916BV18-200BZC		Cypress Semiconductor	18-Mbit DDR-II SRAM 2-Word Burst Architecture		Original	PDF
CY7C1916BV18-250BZC		Cypress Semiconductor	18-Mbit DDR-II SRAM 2-Word Burst Architecture		Original	PDF

CY7C1916BV18 Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
CY7C1316BV18 Abstract: CY7C1318BV18 CY7C1320BV18 CY7C1916BV18 Text: CY7C1316BV18 CY7C1916BV18 CY7C1318BV18 CY7C1320BV18 PRELIMINARY 18-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 • 250-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency	Original	PDF	CY7C1316BV18 CY7C1916BV18 CY7C1318BV18 CY7C1320BV18 18-Mbit 250-MHz CY7C1316BV18 CY7C1318BV18 CY7C1320BV18 CY7C1916BV18
Untitled Abstract: No abstract text available Text: CY7C1316BV18 CY7C1916BV18 CY7C1318BV18 CY7C1320BV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency	Original	PDF	CY7C1316BV18 CY7C1916BV18 CY7C1318BV18 CY7C1320BV18 18-Mbit 300-MHz
CY7C1316BV18 Abstract: CY7C1318BV18 CY7C1320BV18 CY7C1916BV18 Text: CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency	Original	PDF	CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 18-Mbit CY7C1316BV18 CY7C1318BV18 CY7C1320BV18 CY7C1916BV18
CY7C1316BV18 Abstract: CY7C1318BV18 CY7C1320BV18 CY7C1916BV18 Text: CY7C1316BV18 CY7C1916BV18 CY7C1318BV18 CY7C1320BV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency	Original	PDF	CY7C1316BV18 CY7C1916BV18 CY7C1318BV18 CY7C1320BV18 18-Mbit 300-MHz CY7C1316BV18 CY7C1318BV18 CY7C1320BV18 CY7C1916BV18
CY7C1316BV18 Abstract: CY7C1318BV18 CY7C1320BV18 CY7C1916BV18 Text: CY7C1316BV18 CY7C1916BV18 CY7C1318BV18 CY7C1320BV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency	Original	PDF	CY7C1316BV18 CY7C1916BV18 CY7C1318BV18 CY7C1320BV18 18-Mbit 300-MHz CY7C1316BV18 CY7C1318BV18 CY7C1320BV18 CY7C1916BV18
Xilinx spartan xc3s400_ft256 Abstract: XC3S400_FT256 XC3S400PQ208 XC3S250EPQ208 xc3s400TQ144 XC3S400FT256 xc3s1400afg676 XC3S700AFG484 XC3S500EPQ208 XC3S200FT256 Text: Memory Interface Solutions User Guide UG086 v3.3 December 2, 2009 R R Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished,	Original	PDF	UG086 DQS10 DQS11 DQS12 DQS13 DQS14 DQS15 DQS16 DQS17 Xilinx spartan xc3s400_ft256 XC3S400_FT256 XC3S400PQ208 XC3S250EPQ208 xc3s400TQ144 XC3S400FT256 xc3s1400afg676 XC3S700AFG484 XC3S500EPQ208 XC3S200FT256
Untitled Abstract: No abstract text available Text: CY7C1177V18 CY7C1168V18 CY7C1170V18 PRELIMINARY 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • 18-Mbit density (2M x 9, 1M x 18, 512K x 36) • 300 MHz to 400 MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency	Original	PDF	CY7C1177V18 CY7C1168V18 CY7C1170V18 18-Mbit CY7C1177V18/CY7C1168V18/CY7C1170V18
Untitled Abstract: No abstract text available Text: CY7C1316BV18 CY7C1318BV18 CY7C1320BV18 PRELIMINARY 18-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency	Original	PDF	CY7C1316BV18 CY7C1318BV18 CY7C1320BV18 18-Mbit 300-MHz CY7C1916BV18 BB165E BB165D
Untitled Abstract: No abstract text available Text:  CY7C1318BV18, CY7C1320BV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency ■	Original	PDF	CY7C1318BV18, CY7C1320BV18 18-Mbit CY7C1316BV18, CY7C1916BV18, CY7C1320BV18 CY7C1316BV18
CY7C1316BV18 Abstract: CY7C1318BV18 CY7C1320BV18 CY7C1916BV18 Text: CY7C1318BV18, CY7C1320BV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces	Original	PDF	CY7C1318BV18, CY7C1320BV18 18-Mbit CY7C1316BV18 CY7C1318BV18 CY7C1320BV18 CY7C1916BV18
AN5062 Abstract: No abstract text available Text: CY7C1318BV18, CY7C1320BV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces	Original	PDF	CY7C1318BV18, CY7C1320BV18 18-Mbit CY7C1316BV18, CY7C1916BV18, CY7C1320BV18 CY7C1316BV18 AN5062
CY7C1338-100AXC Abstract: gvt7164d32q-6 CY7C1049BV33-12VXC CY7C1363C-133AC CY7C1021DV33-12ZXC CY7C1460AV25-200AXC CY7C1338G-100AC CY7C1041V33-12ZXC CY7C1460V33-200AXC CY7C1021DV33-10ZXC Text: CYPRESS / GALVANTECH # - Connect pin 14 FT pin to Vss CY7C1019BV33-15VC GS71108AJ-12 & - Does not support 1.8V I/O CY7C1019BV33-15VXC GS71108AGJ-12 * - Tie down extra four I/Os with resistor CY7C1019BV33-15ZC GS71108ATP-12 CY7C1019BV33-15ZXC GS71108AGP-12	Original	PDF	CY7C1019BV33-15VC GS71108AJ-12 CY7C1019BV33-15VXC GS71108AGJ-12 CY7C1019BV33-15ZC GS71108ATP-12 CY7C1019BV33-15ZXC GS71108AGP-12 CY7C1019CV33-10VC GS71108AJ-10 CY7C1338-100AXC gvt7164d32q-6 CY7C1049BV33-12VXC CY7C1363C-133AC CY7C1021DV33-12ZXC CY7C1460AV25-200AXC CY7C1338G-100AC CY7C1041V33-12ZXC CY7C1460V33-200AXC CY7C1021DV33-10ZXC
Untitled Abstract: No abstract text available Text:  CY7C1318BV18, CY7C1320BV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture 18-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency	Original	PDF	CY7C1318BV18, CY7C1320BV18 18-Mbit