CY7C1168V18 Search Results

CY7C1168V18 Price and Stock

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Rochester Electronics LLC CY7C1168V18-400BZXC IC SRAM 18MBIT PARALLEL 165FBGA
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CY7C1168V18-400BZXC	Tray	602		7	1 - 10 $43.7 100 $43.7 1000 $43.7 10000 $43.7	Buy Now
Rochester Electronics LLC CY7C1168V18-375BZXC IC SRAM 18MBIT PAR 165FBGA
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CY7C1168V18-375BZXC	Tray	355		6	1 - 10 $57.78 100 $57.78 1000 $57.78 10000 $57.78	Buy Now
Rochester Electronics LLC CY7C1168V18-400BZC IC SRAM 18MBIT PARALLEL 165FBGA
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CY7C1168V18-400BZC	Tray	280		6	1 - 10 $52.63 100 $52.63 1000 $52.63 10000 $52.63	Buy Now
Infineon Technologies AG CY7C1168V18-375BZC IC SRAM 18MBIT PAR 165FBGA
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CY7C1168V18-375BZC	Tray			136	1 - 10 - 100 - 1000 $36.01426 10000 $36.01426	Buy Now
Infineon Technologies AG CY7C1168V18-400BZC IC SRAM 18MBIT PARALLEL 165FBGA
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CY7C1168V18-400BZC	Tray			136	1 - 10 - 100 - 1000 $40.87926 10000 $40.87926	Buy Now

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CY7C1168V18 Datasheets (3)

Part	ECAD Model	Manufacturer	Description	Curated	Type	PDF
CY7C1168V18		Cypress Semiconductor	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)		Original	PDF
CY7C1168V18-375BZC		Cypress Semiconductor	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)		Original	PDF
CY7C1168V18-400BZC		Cypress Semiconductor	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)		Original	PDF

CY7C1168V18 Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
Untitled Abstract: No abstract text available Text: CY7C1166V18 CY7C1177V18 CY7C1168V18 CY7C1170V18 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • 18 Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36) ■ 300 MHz to 400 MHz clock for high bandwidth	Original	PDF	CY7C1166V18 CY7C1177V18 CY7C1168V18 CY7C1170V18 18-Mbit CY7C1166V18, CY7C1177V18, CY7C1168V18, CY7C1170V18 CY7C1166V18)
Untitled Abstract: No abstract text available Text: CY7C1168V18 CY7C1170V18 PRELIMINARY 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • • • • 18-Mbit density (1M x 18, 512K x 36) 300 MHz to 400 MHz clock for high bandwidth 2-Word burst for reducing address bus frequency	Original	PDF	CY7C1168V18 CY7C1170V18 18-Mbit 165-ball
CY7C1166V18 Abstract: CY7C1168V18 CY7C1170V18 CY7C1177V18 Text: CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • 18 Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36) ■ 300 MHz to 400 MHz clock for high bandwidth	Original	PDF	CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18 18-Mbit CY7C1177V18, CY7C1170V18 CY7C1166V18 CY7C1168V18 CY7C1177V18
Untitled Abstract: No abstract text available Text: CY7C1177V18 CY7C1168V18 CY7C1170V18 PRELIMINARY 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • 18-Mbit density (2M x 9, 1M x 18, 512K x 36) • 300 MHz to 400 MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency	Original	PDF	CY7C1177V18 CY7C1168V18 CY7C1170V18 18-Mbit CY7C1177V18/CY7C1168V18/CY7C1170V18
CY7C1166V18 Abstract: CY7C1168V18 CY7C1170V18 CY7C1177V18 Text: CY7C1166V18 CY7C1177V18 CY7C1168V18 CY7C1170V18 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • 18 Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36) ■ 300 MHz to 400 MHz clock for high bandwidth	Original	PDF	CY7C1166V18 CY7C1177V18 CY7C1168V18 CY7C1170V18 18-Mbit CY7C1166V18 CY7C1168V18 CY7C1170V18 CY7C1177V18
3M Touch Systems Abstract: No abstract text available Text: THIS SPEC IS OBSOLETE Spec No: 001-06620 Spec Title: CY7C1166V18/CY7C1177V18/CY7C1168V18/ CY7C1170V18, 18-MBIT DDR-II+ SRAM 2-WORD BURST ARCHITECTURE 2.5 CYCLE READ LATENCY Sunset Owner: Jayasree Nayar (NJY) Replaced by: None CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18	Original	PDF	CY7C1166V18/CY7C1177V18/CY7C1168V18/ CY7C1170V18, 18-MBIT CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18 CY7C1177V18, 3M Touch Systems