CY7C1371D
Abstract: CY7C1373D
Text: PRELIMINARY CY7C1371D CY7C1373D 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero
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Original
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PDF
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CY7C1371D
CY7C1373D
18-Mbit
36/1M
133-MHz
100-MHz
CY7C1371D/CY7C1373D
CY7C1371D
CY7C1373D
|
Untitled
Abstract: No abstract text available
Text: CY7C1371D CY7C1373D 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero
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Original
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PDF
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CY7C1371D
CY7C1373D
18-Mbit
36/1M
133-MHz
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CY7C1371D
Abstract: CY7C1373D CY7C1373D100BZXC
Text: CY7C1371D CY7C1373D 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Supports up to 133-MHz bus operations with zero wait
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Original
|
PDF
|
CY7C1371D
CY7C1373D
18-Mbit
36/1M
133-MHz
CY7C1371D
CY7C1373D
CY7C1373D100BZXC
|
Untitled
Abstract: No abstract text available
Text: CY7C1371D CY7C1373D 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero
|
Original
|
PDF
|
CY7C1371D
CY7C1373D
18-Mbit
36/1M
133-MHz
100-MHz
|
CY7C1371D
Abstract: CY7C1373D
Text: CY7C1371D CY7C1373D 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Supports up to 133-MHz bus operations with zero wait
|
Original
|
PDF
|
CY7C1371D
CY7C1373D
18-Mbit
36/1M
133-MHz
CY7C1371D
CY7C1373D
|