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    CY7C1373D Price and Stock

    Flip Electronics CY7C1373D-133AXI

    IC SRAM 18MBIT PARALLEL 100TQFP
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    DigiKey CY7C1373D-133AXI Tray 1,765 15
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    Infineon Technologies AG CY7C1373D-133AXI

    IC SRAM 18MBIT PARALLEL 100TQFP
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    Avnet Americas CY7C1373D-133AXI 0 Weeks, 2 Days 18
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    Infineon Technologies AG CY7C1373D-100AXC

    IC SRAM 18MBIT PAR 100TQFP
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    Infineon Technologies AG CY7C1373D-133BZI

    IC SRAM 18MBIT PARALLEL 165FBGA
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    Rochester Electronics LLC CY7C1373D-133BZI

    IC SRAM 18MBIT PARALLEL 165FBGA
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    DigiKey CY7C1373D-133BZI Tray 11
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    CY7C1373D Datasheets (27)

    Part ECAD Model Manufacturer Description Curated Type PDF
    CY7C1373D Cypress Semiconductor 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture Original PDF
    CY7C1373D-100AXC Cypress Semiconductor 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture Original PDF
    CY7C1373D-100AXC Cypress Semiconductor 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture Original PDF
    CY7C1373D-100AXC Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 18MBIT 100MHZ 100TQFP Original PDF
    CY7C1373D-100AXCT Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 18MBIT 100MHZ 100TQFP Original PDF
    CY7C1373D-100AXI Cypress Semiconductor 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture Original PDF
    CY7C1373D-100BGC Cypress Semiconductor 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture Original PDF
    CY7C1373D-100BGXC Cypress Semiconductor 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture Original PDF
    CY7C1373D-100BZC Cypress Semiconductor 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture Original PDF
    CY7C1373D-100BZI Cypress Semiconductor 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture Original PDF
    CY7C1373D-100BZXC Cypress Semiconductor 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture Original PDF
    CY7C1373D-100BZXI Cypress Semiconductor 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture Original PDF
    CY7C1373D-133AXC Cypress Semiconductor 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture Original PDF
    CY7C1373D-133AXI Cypress Semiconductor 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture Original PDF
    CY7C1373D-133AXI Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 18MBIT 133MHZ 100TQFP Original PDF
    CY7C1373D-133BGC Cypress Semiconductor 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture Original PDF
    CY7C1373D-133BGI Cypress Semiconductor 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture Original PDF
    CY7C1373D-133BGXC Cypress Semiconductor 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture Original PDF
    CY7C1373D-133BGXI Cypress Semiconductor 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture Original PDF
    CY7C1373D-133BZC Cypress Semiconductor 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture Original PDF

    CY7C1373D Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    CY7C1371D

    Abstract: CY7C1373D
    Text: PRELIMINARY CY7C1371D CY7C1373D 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero


    Original     		PDF CY7C1371D CY7C1373D 18-Mbit 36/1M 133-MHz 100-MHz CY7C1371D/CY7C1373D CY7C1371D CY7C1373D

    Untitled

    Abstract: No abstract text available
    Text: CY7C1371DV25 CY7C1373DV25 PRELIMINARY 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero


    Original     		PDF CY7C1371DV25 CY7C1373DV25 18-Mbit 36/1M 133-MHz 100-MHz

    Untitled

    Abstract: No abstract text available
    Text: CY7C1371D CY7C1373D 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero


    Original     		PDF CY7C1371D CY7C1373D 18-Mbit 36/1M 133-MHz 100-MHz

    Untitled

    Abstract: No abstract text available
    Text: CY7C1371DV25 CY7C1373DV25 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero


    Original     		PDF CY7C1371DV25 CY7C1373DV25 18-Mbit 36/1M 133-MHz 100-MHz CY7C1373DV25

    CY7C1371D-100AXI

    Abstract: CY7C1371D CY7C1373D
    Text: CY7C1371D CY7C1373D 18-Mbit 512K x 36/1Mbit x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles • Supports up to 133-MHz bus operations with zero wait


    Original     		PDF CY7C1371D CY7C1373D 18-Mbit 36/1Mbit 133-MHz CY7C1371D-100AXI CY7C1371D CY7C1373D

    CY7C1371DV25

    Abstract: CY7C1373DV25
    Text: CY7C1371DV25 CY7C1373DV25 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Supports up to 133-MHz bus operations with zero wait


    Original     		PDF CY7C1371DV25 CY7C1373DV25 18-Mbit 36/1M 133-MHz CY7C1371DV25/CY7C1373DV25 CY7C1371DV25 CY7C1373DV25

    662k

    Abstract: CY7C1371DV25 CY7C1371DV25-133AXC CY7C1373DV25
    Text: CY7C1371DV25 CY7C1373DV25 PRELIMINARY 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero


    Original     		PDF CY7C1371DV25 CY7C1373DV25 18-Mbit 36/1M 133-MHz CY7C1371DV25/CY7C1373DV25 662k CY7C1371DV25 CY7C1371DV25-133AXC CY7C1373DV25

    Untitled

    Abstract: No abstract text available
    Text: CY7C1371D CY7C1373D 18-Mbit 512 K x 36/1 M × 18 Flow-Through SRAM with NoBL Architecture 18-Mbit (512 K × 36/1 M × 18) Flow-through SRAM with NoBL™ Architecture Features Functional Description • No Bus Latency (NoBL) architecture eliminates dead cycles


    Original     		PDF CY7C1371D CY7C1373D 18-Mbit 133-MHz

    Untitled

    Abstract: No abstract text available
    Text: CY7C1371D CY7C1373D 18-Mbit 512 K x 36/1 M × 18 Flow-through SRAM with NoBL Architecture 18-Mbit (512 K × 36/1 M × 18) Flow-through SRAM with NoBL™ Architecture Features Functional Description[1] • No Bus Latency (NoBL) architecture eliminates dead


    Original     		PDF CY7C1371D CY7C1373D 18-Mbit CY7C1371D/CY7C1373D

    Untitled

    Abstract: No abstract text available
    Text: CY7C1371D CY7C1373D 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero


    Original     		PDF CY7C1371D CY7C1373D 18-Mbit 36/1M 133-MHz

    Untitled

    Abstract: No abstract text available
    Text: CY7C1371D CY7C1373D 18-Mbit 512 K x 36/1 M × 18 Flow-Through SRAM with NoBL Architecture 18-Mbit (512 K × 36/1 M × 18) Flow-through SRAM with NoBL™ Architecture Features Functional Description • No Bus Latency (NoBL) architecture eliminates dead cycles


    Original     		PDF CY7C1371D CY7C1373D 18-Mbit CY7C1371D/CY7C1373D

    Untitled

    Abstract: No abstract text available
    Text: CY7C1371D CY7C1373D 18-Mbit 512 K x 36/1 M × 18 Flow-through SRAM with NoBL Architecture 18-Mbit (512 K × 36/1 M × 18) Flow-through SRAM with NoBL™ Architecture Features Functional Description • No Bus Latency™ (NoBL™) architecture eliminates dead


    Original     		PDF CY7C1371D CY7C1373D 18-Mbit CY7C1371D/CY7C1373D

    CY7C1371DV25

    Abstract: CY7C1373DV25
    Text: CY7C1371DV25 CY7C1373DV25 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero


    Original     		PDF CY7C1371DV25 CY7C1373DV25 18-Mbit 36/1M 133-MHz CY7C1371DV25 CY7C1373DV25

    CY7C1371DV25

    Abstract: CY7C1373DV25
    Text: CY7C1371DV25 CY7C1373DV25 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero


    Original     		PDF CY7C1371DV25 CY7C1373DV25 18-Mbit 36/1M 133-MHz CY7C1371DV25 CY7C1373DV25

    Untitled

    Abstract: No abstract text available
    Text: CY7C1371D CY7C1373D 18-Mbit 512 K x 36/1 M × 18 Flow-Through SRAM with NoBL Architecture 18-Mbit (512 K × 36/1 M × 18) Flow-through SRAM with NoBL™ Architecture Features Functional Description • No Bus Latency (NoBL) architecture eliminates dead cycles


    Original     		PDF CY7C1371D CY7C1373D 18-Mbit CY7C1371D/CY7C1373D

    CY7C1371D

    Abstract: CY7C1373D CY7C1373D100BZXC
    Text: CY7C1371D CY7C1373D 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Supports up to 133-MHz bus operations with zero wait


    Original     		PDF CY7C1371D CY7C1373D 18-Mbit 36/1M 133-MHz CY7C1371D CY7C1373D CY7C1373D100BZXC

    Untitled

    Abstract: No abstract text available
    Text: CY7C1371D CY7C1373D 18-Mbit 512 K x 36/1 M × 18 Flow-Through SRAM with NoBL Architecture 18-Mbit (512 K × 36/1 M × 18) Flow-through SRAM with NoBL™ Architecture Functional Description Features • No Bus Latency (NoBL) architecture eliminates dead cycles


    Original     		PDF CY7C1371D CY7C1373D 18-Mbit 133-MHz

    CY7C1371D

    Abstract: CY7C1373D
    Text: CY7C1371D CY7C1373D 18-Mbit 512 K x 36/1 M × 18 Flow-through SRAM with NoBL Architecture 18-Mbit (512 K × 36/1 M × 18) Flow-through SRAM with NoBL™ Architecture Features Functional Description • No Bus Latency™ (NoBL™) architecture eliminates dead


    Original     		PDF CY7C1371D CY7C1373D 18-Mbit 133-MHz CY7C1371D CY7C1373D

    Untitled

    Abstract: No abstract text available
    Text: CY7C1371D CY7C1373D 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero


    Original     		PDF CY7C1371D CY7C1373D 18-Mbit 36/1M 133-MHz 100-MHz

    Untitled

    Abstract: No abstract text available
    Text: CY7C1371DV25 CY7C1373DV25 PRELIMINARY 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero


    Original     		PDF CY7C1371DV25 CY7C1373DV25 18-Mbit 36/1M 133-MHz 117-MHz 100-MHz

    CY7C1371D

    Abstract: CY7C1373D
    Text: CY7C1371D CY7C1373D 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Supports up to 133-MHz bus operations with zero wait


    Original     		PDF CY7C1371D CY7C1373D 18-Mbit 36/1M 133-MHz CY7C1371D CY7C1373D

    CY7C1371D

    Abstract: CY7C1373D
    Text: CY7C1371D CY7C1373D 18-Mbit 512 K x 36/1 M × 18 Flow-through SRAM with NoBL Architecture 18-Mbit (512 K × 36/1 M × 18) Flow-through SRAM with NoBL™ Architecture Features Functional Description[1] • No Bus Latency (NoBL) architecture eliminates dead


    Original     		PDF CY7C1371D CY7C1373D 18-Mbit 133-MHz CY7C1371D CY7C1373D

    CY7C1338-100AXC

    Abstract: gvt7164d32q-6 CY7C1049BV33-12VXC CY7C1363C-133AC CY7C1021DV33-12ZXC CY7C1460AV25-200AXC CY7C1338G-100AC CY7C1041V33-12ZXC CY7C1460V33-200AXC CY7C1021DV33-10ZXC
    Text: CYPRESS / GALVANTECH # - Connect pin 14 FT pin to Vss CY7C1019BV33-15VC GS71108AJ-12 & - Does not support 1.8V I/O CY7C1019BV33-15VXC GS71108AGJ-12 * - Tie down extra four I/Os with resistor CY7C1019BV33-15ZC GS71108ATP-12 CY7C1019BV33-15ZXC GS71108AGP-12


    Original     		PDF CY7C1019BV33-15VC GS71108AJ-12 CY7C1019BV33-15VXC GS71108AGJ-12 CY7C1019BV33-15ZC GS71108ATP-12 CY7C1019BV33-15ZXC GS71108AGP-12 CY7C1019CV33-10VC GS71108AJ-10 CY7C1338-100AXC gvt7164d32q-6 CY7C1049BV33-12VXC CY7C1363C-133AC CY7C1021DV33-12ZXC CY7C1460AV25-200AXC CY7C1338G-100AC CY7C1041V33-12ZXC CY7C1460V33-200AXC CY7C1021DV33-10ZXC

    um61256

    Abstract: PM25LV040 SST25LF040B Pm25LV016 PM25LV010A PM25LV080 SST25LF512A HY514264 M5M418 hynix hy57v281620
    Text: Cross Reference Your Memory Supplier part number brand AMIC part number Description µPD4218165 µPD4218165 µPD424260 µPD431000A µPD43256B µPD441000L-B µPD442000L-B µPD442012L-XB µPD444012L-B A29F002 AM29DL162C/D AM29DL163C/D AM29DL164C/D AM29F002B


    Original     		PDF PD4218165 PD424260 PD431000A PD43256B PD441000L-B PD442000L-B PD442012L-XB PD444012L-B A29F002 um61256 PM25LV040 SST25LF040B Pm25LV016 PM25LV010A PM25LV080 SST25LF512A HY514264 M5M418 hynix hy57v281620