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    CK COMPONENTS Search Results

    CK COMPONENTS Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    74HC4053FT Toshiba Electronic Devices & Storage Corporation CMOS Logic IC, SPDT(1:2)/Analog Multiplexer, TSSOP16B, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation
    XPQR8308QB Toshiba Electronic Devices & Storage Corporation N-ch MOSFET, 80 V, 350 A, 0.00083 Ω@10V, L-TOGL Visit Toshiba Electronic Devices & Storage Corporation
    TRS8E65H Toshiba Electronic Devices & Storage Corporation SiC Schottky Barrier Diode (SBD), 650 V, 8 A, TO-220-2L Visit Toshiba Electronic Devices & Storage Corporation
    TCKE800NA Toshiba Electronic Devices & Storage Corporation eFuse IC (electronic Fuse), 4.4 to 18 V, 5.0 A, Auto-retry, WSON10B Visit Toshiba Electronic Devices & Storage Corporation
    7UL2T125FK Toshiba Electronic Devices & Storage Corporation One-Gate Logic(L-MOS), Buffer, SOT-765 (US8), -40 to 85 degC Visit Toshiba Electronic Devices & Storage Corporation
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    CK COMPONENTS Price and Stock

    C&K A11003RNCQ

    Rotary Switches Rotary
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    TTI A11003RNCQ Each 72
    • 1 -
    • 10 -
    • 100 $7.47
    • 1000 $5.82
    • 10000 $5.82
    Buy Now

    C&K 7103SYZBE

    Toggle Switches ON-OFF-ON SPDT SLDR
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    TTI 7103SYZBE Kit 100
    • 1 -
    • 10 -
    • 100 $5.66
    • 1000 $5.66
    • 10000 $5.66
    Buy Now

    C&K 7101SD9V3BE

    Toggle Switches ON-ON SPDT SEALED PC
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    TTI 7101SD9V3BE Each 80
    • 1 -
    • 10 -
    • 100 $6.62
    • 1000 $6.23
    • 10000 $6.11
    Buy Now

    CK COMPONENTS Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    84x4

    Abstract: No abstract text available
    Text: 256Mb sTSOPII DDR SDRAM Key Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe DQS • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition


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    PDF 256Mb 4K/64ms 54pin 31/VREF-0 84x4

    Untitled

    Abstract: No abstract text available
    Text: 256Mb DDR SDRAM Key Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe DQS • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition


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    PDF 256Mb 8K/64ms

    Untitled

    Abstract: No abstract text available
    Text: Preliminary DDR SDRAM 256Mb Key Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe DQS • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition


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    PDF 256Mb 8K/64ms 31/VREF-0

    DDR200

    Abstract: DDR266 DDR333 256mb ddr333 200 pin K4H560438D
    Text: 256Mb sTSOPII DDR SDRAM Key Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe DQS • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition


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    PDF 256Mb 8K/64ms 54pin DDR200 DDR266 DDR333 256mb ddr333 200 pin K4H560438D

    K4H5

    Abstract: K4H561638D 256mb ddr333 200 pin K4H561638D-TC
    Text: 256Mb DDR SDRAM Key Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe DQS • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition


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    PDF 256Mb 8K/64ms 66pin K4H5 K4H561638D 256mb ddr333 200 pin K4H561638D-TC

    CL25

    Abstract: No abstract text available
    Text: 256Mb DDR SDRAM Key Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe DQS • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition


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    PDF 256Mb 4K/64ms 66pin 31/VREF-0 CL25

    256mb ddr333 200 pin

    Abstract: DDR266 DDR266A DDR266B DDR333 K4H560438D-GC K4H561638D
    Text: 256Mb DDR SDRAM Key Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe DQS • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition


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    PDF 256Mb 8K/64ms 256mb ddr333 200 pin DDR266 DDR266A DDR266B DDR333 K4H560438D-GC K4H561638D

    12v AC to DC CIRCUIT DIAGRAM

    Abstract: No abstract text available
    Text: 256Mb DDR SDRAM Key Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe DQS • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition


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    PDF 256Mb 8K/64ms 31/VREF 12v AC to DC CIRCUIT DIAGRAM

    48MHZ

    Abstract: CK-408 CY28324 SSOP-48 845 vrm circuit diagram intel 845
    Text: CY28324 PRELIMINARY FTG for Intel Pentium® 4 CPU and Chipsets Features ® • Compatible to Intel CK-00, CK-Titan & CK-408 Clock Synthesizer/Driver Specifications • System frequency synthesizer for Intel 850, Brookdale 845 and Brookdale - G Pentium® 4 Chipsets


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    PDF CY28324 CK-00, CK-408 CY28324 48MHZ SSOP-48 845 vrm circuit diagram intel 845

    48MHZ

    Abstract: CK-408 CY28324 SSOP-48
    Text: CY28324 PRELIMINARY FTG for Intel Pentium® 4 CPU and Chipsets Features ® • Compatible to Intel CK-00, CK-Titan & CK-408 Clock Synthesizer/Driver Specifications • System frequency synthesizer for Intel 850, Brookdale 845 and Brookdale - G Pentium® 4 Chipsets


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    PDF CY28324 CK-00, CK-408 CY28324 48MHZ SSOP-48

    CK-408

    Abstract: CY28324 SSOP-48 48MHZ
    Text: CY28324 PRELIMINARY FTG for Intel Pentium® 4 CPU and Chipsets Features ® • Compatible to Intel CK-00, CK-Titan & CK-408 Clock Synthesizer/Driver Specifications • System frequency synthesizer for Intel 850, Brookdale 845 and Brookdale - G Pentium® 4 Chipsets


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    PDF CY28324 CK-00, CK-408 CY28324 SSOP-48 48MHZ

    48MHZ

    Abstract: CK-408 CY28324 SSOP-48 105839
    Text: CY28324 PRELIMINARY FTG for Intel Pentium 4 CPU and Chipsets Features • Compatible to Intel CK-00, CK-Titan & CK-408 Clock Synthesizer/Driver Specifications • System frequency synthesizer for Intel Pentium® 4 clasee processor • Programmable clock output frequency with less than 1


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    PDF CY28324 CK-00, CK-408 CY28324 48MHZ SSOP-48 105839

    DDR200

    Abstract: DDR266 DDR333 W3EG6433S-AD4
    Text: W3EG6433S-AD4 -BD4 White Electronic Designs PRELIMINARY* 256MB - 32Mx64 DDR SDRAM UNBUFFERED, w/PLL FEATURES DESCRIPTION „ DDR200, DDR266 and DDR333 „ Double-data-rate architecture „ Bi-directional data strobes DQS „ Differential clock inputs (CK & CK#)


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    PDF W3EG6433S-AD4 256MB 32Mx64 DDR200, DDR266 DDR333 W3EG6433S 32Mx8 DDR200 DDR333 W3EG6433S-AD4

    Untitled

    Abstract: No abstract text available
    Text: White Electronic Designs W3EG72125S-D3 -JD3 -AJD3 PRELIMINARY 1GB - 128Mx72 DDR SDRAM REGISTERED ECC w/PLL FEATURES DESCRIPTION Double-data-rate architecture Clock Speeds of 100MHz, 133MHz and 166MHz Bi-directional data strobes DQS Differential clock inputs (CK & CK#)


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    PDF W3EG72125S-D3 128Mx72 100MHz, 133MHz 166MHz W3EG72125S 256Mb 128Mx4

    Untitled

    Abstract: No abstract text available
    Text: CY25823 CK-SSCD Spread Spectrum Differential Clock Specification CK-SSCD Spread Spectrum Differential Clock Specification Features • 3.3 V operation ■ 96- and 100-MHz frequency support ■ Selectable slew rate control ■ 200-ps jitter ■ I2C programmability


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    PDF CY25823 100-MHz 16-pin 200-ps

    EM47FM0888SBA

    Abstract: No abstract text available
    Text: EM47FM0888SBA 4Gb 64Mx8Bank×8 Double DATA RATE 3 low voltage SDRAM Features Description • JEDEC Standard VDD/VDDQ = 1.5V±0.075V • All inputs and outputs are compatible with SSTL_15 interface. • Fully differential clock inputs (CK, /CK) operation.


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    PDF EM47FM0888SBA 78Ball-FBGA EM47FM0888SBA

    DDR200

    Abstract: DDR266 DDR333 W3EG72125S-D3
    Text: White Electronic Designs W3EG72125S-D3 -JD3 -AJD3 PRELIMINARY* 1GB - 2x64Mx72 DDR SDRAM REGISTERED ECC w/PLL FEATURES DESCRIPTION Double-data-rate architecture Clock Speeds of 100MHz, 133MHz and 166MHz Bi-directional data strobes DQS Differential clock inputs (CK & CK#)


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    PDF W3EG72125S-D3 2x64Mx72 100MHz, 133MHz 166MHz W3EG72125S 256Mb 2x64Mx4 DDR200 DDR266 DDR333 W3EG72125S-D3

    EM47FM0888MBA

    Abstract: No abstract text available
    Text: EM47FM0888MBA 4Gb 64Mx8Bank×8 Double DATA RATE 3 low voltage SDRAM Features Description • JEDEC Standard VDD/VDDQ = 1.35V(1.283-1.45V) • All inputs and outputs are compatible with SSTL_15 interface. • Fully differential clock inputs (CK, /CK) operation.


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    PDF EM47FM0888MBA 78Ball-FBGA EM47FM0888MBA

    c28k OMRON Operation Manual

    Abstract: C200H Pro27 OMRON Operation Manual c28k programming manual omron C60k cables pin diagram OMRON PRO27 programming console C28H OMRON Operation Manual password omron c500 pro 13 Omron Programming Console PRO 27 omron c500 pro 13 OMRON LSS 3 manual
    Text: Issued March 1997 232-3945 Data Pack D Data Sheet RS Omron CK range programmable logic controllers PLCs The Omron CK PLCs are a high specification, cost effective, compact range of programmable logic controllers (PLCs) which enable very flexible systems to


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    DDR200

    Abstract: DDR266 DDR333 W3EG64128S-AD4
    Text: W3EG64128S-AD4 -BD4 White Electronic Designs PRELIMINARY* 1GB – 2x64Mx64 DDR SDRAM UNBUFFERED w/PLL FEATURES DESCRIPTION „ Double-data-rate architecture „ Bi-directional data strobes DQS „ Differential clock inputs (CK & CK#) „ Programmable Read Latency 2,2.5 (clock)


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    PDF W3EG64128S-AD4 2x64Mx64 W3EG64128S 512Mb 128Mx8 DDR200 DDR266 DDR333 W3EG64128S-AD4

    UFG-C1

    Abstract: CK-408 CY28322-2
    Text: PRELIMINARY CY28322-2 133-MHz Spread Spectrum Clock Synthesizer with Differential CPU Outputs Features Benefits  • Compliant with Intel CK-Titan and CK-408 clock synthesizer/driver specifications Supports next generation Pentium processors using differential clock drivers


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    PDF CY28322-2 133-MHz CK-408 48-MHz CY28322-2 UFG-C1

    schematic diagram of TV memory writer

    Abstract: c28k OMRON Operation Manual C200H Pro27 OMRON Operation Manual OMRON PRO27 programming console C28H OMRON Operation Manual omron C60k cables pin diagram C20K-ETL01 Omron Programming Console PRO 27 omron c500 pro 13 C200H Pro27
    Text: Issued March 1993 014-964 Data Pack D Data Sheet RS Omron CK range programmable logic controllers PLCs The Omron CK PLCs are a high specification, cost effective, compact range of programmable logic controllers (PLCs) which enable very flexible systems to


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    PDF

    samsung 5230

    Abstract: DDR200 DDR266 DDR333 W3EG72125S-D3
    Text: White Electronic Designs W3EG72125S-D3 -JD3 -AJD3 PRELIMINARY* 1GB – 2x64Mx72 DDR SDRAM REGISTERED ECC w/PLL FEATURES DESCRIPTION Double-data-rate architecture Clock Speeds of 100MHz, 133MHz and 166MHz Bi-directional data strobes DQS Differential clock inputs (CK & CK#)


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    PDF W3EG72125S-D3 2x64Mx72 100MHz, 133MHz 166MHz W3EG72125S 256Mb 2x64Mx4 samsung 5230 DDR200 DDR266 DDR333 W3EG72125S-D3

    Untitled

    Abstract: No abstract text available
    Text: EM47FM0888MBA 4Gb 64Mx8Bank×8 Double DATA RATE 3 low voltage SDRAM Features Description • JEDEC Standard VDD/VDDQ = 1.35V(1.283-1.45V) • All inputs and outputs are compatible with SSTL_15 interface. • Fully differential clock inputs (CK, /CK) operation.


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    PDF EM47FM0888MBA 78Ball-FBGA