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    BLOCK DIAGRAM OF PECL TO TTL Search Results

    BLOCK DIAGRAM OF PECL TO TTL Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    SNJ5480J Rochester Electronics LLC Adder/Subtractor, TTL, CDIP14, Visit Rochester Electronics LLC Buy
    5480FM Rochester Electronics LLC 5480 - Multiplier, TTL, CDFP14 Visit Rochester Electronics LLC Buy
    9317CDC Rochester Electronics LLC 9317 - Decoder/Driver, TTL, CDIP16 Visit Rochester Electronics LLC Buy
    54H62FM Rochester Electronics LLC 54H62 - Gate, TTL, CDFP14 Visit Rochester Electronics LLC Buy
    5496J/B Rochester Electronics LLC 5496 - Shift Register, 5-Bit, TTL Visit Rochester Electronics LLC Buy

    BLOCK DIAGRAM OF PECL TO TTL Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: VSC834 Data Sheet FEATURES ● ● ● ● ● 17 input by 17 output crosspoint switch 2.7 Gbps NRZ data bandwidth 46 Gbps aggregate bandwidth TTL-compatible µP interface Differential PECL data inputs ● ● ● ● ● On-chip 50 Ω input terminations


    Original     		PDF VSC834 256-pin VSC834 17x17 G52247-0 J-STD-020.

    lcd Voltmeter

    Abstract: CXA3197 HI3197 HI3197JCQ C2274
    Text: HI3197 Data Sheet October 1998 10-Bit, 125 MSPS D/A Converter • Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Bits • Conversion Rate HI3197JCQ -20 to 75 125 MSPS PECL 100 MSPS (TTL) • Data Input Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TTL


    Original     		PDF HI3197 10-Bit, HI3197JCQ 400mW lcd Voltmeter CXA3197 HI3197 HI3197JCQ C2274

    PRL-426TTR

    Abstract: PRL-426N PRL426PTR PRL-426T PRL-426 sma
    Text: PRL-426N DUAL CHANNEL NECL TO LVDS TRANSLATOR PRL-426P DUAL CHANNEL PECL TO LVDS TRANSLATOR PRL-426T DUAL CHANNEL TTL TO LVDS TRANSLATOR APPLICATIONS • Converting Single Ended or Differential NECL/PECL Signals to LVDS Signals • Converting TTL Signals to LVDS


    Original     		PDF PRL-426N PRL-426P PRL-426T PRL-426NTR, PRL-426PTR PRL-426TTR PRL-426NTR PRL-425N PRL-426 PRL-426TTR PRL426PTR PRL-426 sma

    AZ100ELT23

    Abstract: No abstract text available
    Text: AZ100ELT23 Dual Differential PECL to CMOS/TTL Translator www.azmicrotek.com DESCRIPTION The AZ100ELT23 is a dual differential PECL to CMOS/TTL translator. Because PECL Positive ECL levels are used, only VCC and ground are required. The small outline 8-lead packaging and the low skew, dual gate


    Original     		PDF AZ100ELT23 AZ100ELT23 MC100ELT23 500ps

    AZ100ELT20

    Abstract: ARIZONA MICROTEK MLP8
    Text: AZ100ELT20 CMOS/TTL to Differential PECL Translator www.azmicrotek.com DESCRIPTION FEATURES The AZ100ELT20 is a CMOS/TTL to differential PECL translator. It operates with a single power supply of +3.0 to +5.5 volts, making it ideal for both LVCMOS/LVTTL and CMOS/TTL applications. The extremely


    Original     		PDF AZ100ELT20 AZ100ELT20 MC100ELT20, MC100LVELT20 SY89329V ARIZONA MICROTEK MLP8

    ARIZONA MICROTEK

    Abstract: MARKING HT23
    Text: AZ100ELT23 Dual Differential PECL to CMOS/TTL Translator www.azmicrotek.com DESCRIPTION The AZ100ELT23 is a dual differential PECL to CMOS/TTL translator. Because PECL Positive ECL levels are used, only VCC and ground are required. The small outline 8-lead packaging and the low skew, dual gate


    Original     		PDF AZ100ELT23 AZ100ELT23 MC100ELT23 500ps ARIZONA MICROTEK MARKING HT23

    AZ100ELT22

    Abstract: ARIZONA MICROTEK
    Text: AZ100ELT22 Dual CMOS/TTL to Differential PECL Translator DESCRIPTION The AZ100ELT22 is a dual CMOS/TTL to differential PECL translator. Because PECL Positive ECL levels are used, only VCC and ground are required. The small outline packaging and the low skew, dual gate design of


    Original     		PDF AZ100ELT22 AZ100ELT22 MC100ELT22, MC100LVELT22 SY89322V 100ps ARIZONA MICROTEK

    AZ100ELT21

    Abstract: ARIZONA MICROTEK
    Text: AZ100ELT21 Differential PECL to CMOS/TTL Translator DESCRIPTION The AZ100ELT21 is a differential PECL to CMOS/TTL translator. Because PECL Positive ECL levels are used, only VCC and ground are required. The small outline 8-lead packaging and the single gate of the


    Original     		PDF AZ100ELT21 AZ100ELT21 MC100ELT21 ARIZONA MICROTEK

    F100K

    Abstract: SY100S391 SY100S391FC SY100S391JC SY100S391JCTR
    Text: LOW-POWER HEX TTL-TO-PECL TRANSLATOR FEATURES DESCRIPTION The SY100S391 is a hex TTL-to-PECL translator for converting TTL logic levels to 100K logic levels. The unique feature of this translator is the ability to do this translation using only one +5V supply. The differential outputs allow


    Original     		PDF SY100S391 grF24-1 SY100S391JC J28-1 SY100S391JCTR SY100S391 F24-1) F100K SY100S391FC SY100S391JC SY100S391JCTR

    Untitled

    Abstract: No abstract text available
    Text: LOW-POWER HEX TTL-TO-PECL TRANSLATOR FEATURES DESCRIPTION The SY100S391 is a hex TTL-to-PECL translator for converting TTL logic levels to 100K logic levels. The unique feature of this translator is the ability to do this translation using only one +5V supply. The differential outputs allow


    Original     		PDF SY100S391 SY100S391JC J28-1 SY100S391JCTR SY100S391 F24-1) J28-1)

    Untitled

    Abstract: No abstract text available
    Text: CTS100ELT22 Dual CMOS/TTL to Differential PECL Translator MSOP8, SOIC8 Block Diagram Features      0.5ns Typical Propogation Delay <100ps Typical Output to Output Skew Flow Through Pinouts Differential PECL Output RoHS Compliant Pb Free Packages


    Original     		PDF CTS100ELT22 100ps CTS100ELT22 MC100ELT22, MC100LVELT22 SY89322V. RevA1113

    93C46

    Abstract: ML6510 ML6510CQ80
    Text: www.fairchildsemi.com ML6510 Series Programmable Adaptive Clock Manager PACMan Features General Description • Input clocks can be either TTL or PECL with low input to output clock phase error • 8 independent, automatically deskewed clock outputs with up to 5ns of on-board deskew range (10ns round trip)


    Original     		PDF ML6510 80MHz 500ps DS30006510 93C46 ML6510 ML6510CQ80

    Untitled

    Abstract: No abstract text available
    Text: CTS100ELT23 Dual Differential PECL to CMOS/TTL Translator MSOP8, SOIC8 Features Block Diagram   3.5ns Typical Propagation Delay <500ps Typical Output to Output Skew  Differential PECL Inputs  Flow Through Pinouts  CMOS/TTL Outputs  RoHS Compliant Pb Free Packages


    Original     		PDF CTS100ELT23 500ps CTS100ELT23 MC100ELT23. RevA1113 CTS100ELT23DG

    AZM100ELT20

    Abstract: AZHLT20 AZ100ELT20 AZ100ELT20D AZ100ELT20DR1 AZ100ELT20DR2 AZ10ELT20 AZ10ELT20D AZ10ELT20DR1 AZ10ELT20DR2
    Text: ARIZONA MICROTEK, INC. AZ10ELT20 AZ100ELT20 CMOS/TTL to Differential PECL Translator PACKAGE AVAILABILITY FEATURES • • • • • • 0.5ns Typical Propagation Delay Differential PECL Outputs Flow Through Pinouts Operating Range of 3.0V to 5.5V Direct Replacement for ON Semiconductor


    Original     		PDF AZ10ELT20 AZ100ELT20 MC10ELT20 MC100ELT20 AZ10ELT20D AZ10ELT20DR1 AZ10ELT20DR2 AZ100ELT20D AZ100ELT20DR1 AZ100ELT20DR2 AZM100ELT20 AZHLT20 AZ100ELT20 AZ100ELT20D AZ100ELT20DR1 AZ100ELT20DR2 AZ10ELT20 AZ10ELT20D AZ10ELT20DR1 AZ10ELT20DR2

    AZ100ELT20

    Abstract: AZ100ELT20D AZ100ELT20DR1 AZ100ELT20DR2 AZ10ELT20 AZ10ELT20D AZ10ELT20DR1 AZ10ELT20DR2 MC100ELT20 MC10ELT20
    Text: ARIZONA MICROTEK, INC. AZ10ELT20 AZ100ELT20 CMOS/TTL to Differential PECL Translator PACKAGE AVAILABILITY FEATURES • • • • • • 0.5ns Typical Propagation Delay Differential PECL Outputs Flow Through Pinouts Operating Range of +3.0V to +5.5V Direct Replacement for ON Semiconductor


    Original     		PDF AZ10ELT20 AZ100ELT20 MC10ELT20 MC100ELT20 AZ10ELT20D AZ10ELT20DR1 AZ10ELT20DR2 AZ100ELT20D AZ100ELT20DR1 AZ100ELT20DR2 AZ100ELT20 AZ100ELT20D AZ100ELT20DR1 AZ100ELT20DR2 AZ10ELT20 AZ10ELT20D AZ10ELT20DR1 AZ10ELT20DR2 MC100ELT20 MC10ELT20

    H607

    Abstract: SY100H607 SY100H607JC SY10H607 SY10H607JC SY10H607JCTR
    Text: REGISTERED HEX PECL-TO-TTL FEATURES DESCRIPTION Differential PECL data and clock inputs 48mA sink, 15mA source TTL outputs Single +5V power supply Multiple power and ground pins to minimize noise Specified within-device skew VBB output for single-ended use


    Original     		PDF MC10H/100H607 28-pin SY10/100H607 SY10H607JC J28-1 SY10H607JCTR SY100H607JC SY100H607JCTR H607 SY100H607 SY100H607JC SY10H607 SY10H607JC SY10H607JCTR

    F100K

    Abstract: SY100S391 SY100S391JC SY100S391JCTR
    Text: LOW-POWER HEX TTL-TO-PECL TRANSLATOR Micrel, Inc. FEATURES • ■ ■ ■ SY100S391 SY100S391 DESCRIPTION The SY100S391 is a hex TTL-to-PECL translator for converting TTL logic levels to 100K logic levels. The unique feature of this translator is the ability to do this translation


    Original     		PDF SY100S391 SY100S391 M9999-042307 F100K SY100S391JC SY100S391JCTR

    Untitled

    Abstract: No abstract text available
    Text: VITESSE G-TAXIchips VSC7101 /V5C7 702/VSC7103/VSC7 704 1.25 Gbits/sec Data Communications Chipset G-TAXICHIP FEATURES • Compatible with ANSI X3T9.3 Fiber Channel Standard • Up to 1.25 Gbits/sec serial data rate • 32 or 40-bit wide parallel TTL data bus input


    OCR Scan     		PDF VSC7101 702/VSC7103/VSC7 40-bit 8B/10B

    COMMAND40

    Abstract: No abstract text available
    Text: VITESSE VSC7103/V5C7104 High Performance M u x /D e m u x Chipset for Fibre Channel or Proprietary Serial Links MUX/DMUX FEATURES • Parallel 32 or 40-bit wide TTL bus interface • 32 or40-to-10 mux • 10-to-32 or 40 demux • Encode/decode functions and special


    OCR Scan     		PDF 40-bit or40-to-10 10-to-32 8B/10B X3T11 VSC7103/V5C7104 0G0123b V5C7103/ V5C7104 VSC7103 COMMAND40

    ttl 741

    Abstract: No abstract text available
    Text: Advance Product Information 2.5 Gbits/sec Dual 2x2 Crosspoint Switch VSC830 Features • Dual 2x2 Crosspoint Switch • PECL Compatible Output Driver • 2.9 Gbits/sec NRZ Data Bandwidth, 2.9 GHz Signal Bandwidth • PECL/TTL Compatible Control Inputs • Back-terminated Output Driver


    OCR Scan     		PDF VSC830 VSC830 G52192-0, ttl 741

    Untitled

    Abstract: No abstract text available
    Text: « 01/Iie n /« V LOW-POWER HEX PECL-TO-TTL TRANSLATOR SYNERGY SEMICONDUCTOR FEATURES PRELIMINARY SY100S390 DESCRIPTION The SY100S390 is a hex PECL-to-TTL translator for converting 100K logic levels to TTL logic levels. Unlike other level translators, the SY100S390 operates using only one


    OCR Scan     		PDF 01/Iie SY100S390 SY100S390 28-pin T0Q13fil

    Untitled

    Abstract: No abstract text available
    Text: * SINGLE SUPPLY 1:9 PECL/TTL-TO-PECL SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION • PECL version of popular ECLinPS E111 ■ Low skew ■ Guaranteed skew spec ■ V bb output ■ TTL enable input ■ Selectable TTL or PECL clock input ■ Single +5V supply


    OCR Scan     		PDF SY100S811 Z28-1 SY100S8e SY100S811JC J28-1 SY100S811JCTR SY100S811ZC Z16-1 SY100S811ZCTR

    Untitled

    Abstract: No abstract text available
    Text: SYNERGY SEMICONDUCTOR SINGLE SUPPLY PECL Clockworks 1:9 CLOCK DRIVER " " ly 'S i FEATURES DESCRIPTION • PECL version of popular ECLinPS E111 ■ Low skew ■ Guaranteed skew spec ■ V bb output ■ TTL enable input ■ Selectable TTL or PECL clock input


    OCR Scan     		PDF 75Ki2 SY100S811JC J28-1

    wo-04

    Abstract: F100K SY100S391 SY100S391DC SY100S391FC
    Text: LOW-POWER HEX TTL-TO-PECL TRANSLATOR r c ^ L . I riM lM o LA I U r i SYNERGY SEMICONDUCTOR FEATURES SY100S391 DESCRIPTION • Operates from a single +5V supply ■ Differential PECL outputs ■ ESD protection of 2000V The SY100S391 is a hex TTL-to-PECL translator for


    OCR Scan     		PDF SY100S391 SY100S390 F100K SY100S391 CI013fl SY100S391DC D24-1 SY100S391FC wo-04 F100K