toshiba tlc 711
Abstract: RDRAM Clock T3D Toshiba
Text: TO SH IB A T E N T A T IV E TC59RM716 8 MB/RB T O S H IB A M O S D IG IT A L IN T E G R A T E D C IR C U IT SILIC O N M O N O L IT H IC Overview The Direct R a m b u s T M DRAM (Direct RDRAMTM) is a general-purpose high performance memory device suitable for use in a broad range of applications including computer memory, graphics, video
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TC59RM716
128/144-Mbit
600-MHz
800-MHz
P-TFBGA62-1312-0
toshiba tlc 711
RDRAM Clock
T3D Toshiba
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Am29337
Abstract: No abstract text available
Text: Am29337 16-Bit Bounds Checker Double Comparator Out-of-Bounds Flag - C om pares a 16-bit input num ber with a low er lim it and an upper limit - Flags values th a t are outside the bounds of a lower and an upper limit Cascadable Compares Signed or Unsigned Numbers
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Am29337
16-Bit
28-Pin
WF023040
ICR00480
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IS43R32800
Abstract: 43R32800
Text: IS43R32800 8Mx32 256Mb DDR Synchronous DRAM FEATURES • Vdd/Vddq=2.5V+0.2V -5, -6, -75 • Double data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data • Differential clock input (CLK and /CLK)
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IS43R32800
8Mx32
256Mb
IS43R32800
144-Ball)
43R32800
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IS46R32800B
Abstract: 46R32800B
Text: IS46R32800B 8Mx32 256Mb DDR Synchronous DRAM FEATURES • Vdd/Vddq=2.5V+0.2V -6, -75 • Double data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data • Differential clock input (CLK and /CLK)
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IS46R32800B
8Mx32
256Mb
IS46R32800B
46R32800B
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Untitled
Abstract: No abstract text available
Text: IS46R32800B 8Mx32 256Mb DDR Synchronous DRAM FEATURES • VDD/VDDQ=2.5V+0.2V -6, -75 • Double data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data • Differential clock input (CLK and /CLK)
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IS46R32800B
8Mx32
256Mb
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Untitled
Abstract: No abstract text available
Text: IS43R32800B 8Mx32 256Mb DDR Synchronous DRAM FEATURES • VDD/VDDQ=2.5V+0.2V -5, -6, -75 • Double data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data • Differential clock input (CLK and /CLK)
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IS43R32800B
8Mx32
256Mb
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IS43R32800B
Abstract: 43R32800B IS43R32800 IS43R32800B-75BI IS43R32800B-5B
Text: IS43R32800B 8Mx32 256Mb DDR Synchronous DRAM FEATURES • Vdd/Vddq=2.5V+0.2V -5, -6, -75 • Double data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data • Differential clock input (CLK and /CLK)
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IS43R32800B
8Mx32
256Mb
IS43R32800B
43R32800B
IS43R32800
IS43R32800B-75BI
IS43R32800B-5B
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Untitled
Abstract: No abstract text available
Text: IS43R32800 8Mx32 256Mb DDR Synchronous DRAM FEATURES • VDD/VDDQ=2.5V+0.2V -5, -6, -75 • Double data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data • Differential clock input (CLK and /CLK)
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IS43R32800
8Mx32
256Mb
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00D05
Abstract: No abstract text available
Text: MITSUBISHI LSIs MH1M09AOJ-8,-10,-12/ MHlM09A0JA-8,-10,-12 FAST PAGE MODE 1048576-W 0RD BY 9-BIT DYNAMIC RAM DESCRIPTION PIN CONFIGURATION TOP VIEW The M H 1M 09A0J, J A is 1048576 word x 9 b it dynam ic RAM and consists o f nine industry standard 1M x 1 d y
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048576-W
09A0J,
MH1M09A
MHlM09A0J
M5M41000AJ
M5M41000AJ
-12/MH1M09A0JA-8,
1O48576-W
MH1M09A0J-8,
12/MH1M09A0
00D05
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8080a intel microprocessor Architecture Diagram
Abstract: Z8530 ABOTT microprocessor 80286 AM7960 SDLC scc pll TTPC CRC-16 Z8000 Z8030
Text: Z8030/Z8530 H Z8030/Z8530(H) Serial Communications Controller DISTINCTIVE CHARACTERISTICS T w o 0 to 2 M bps fu ll d u p le x se ria l ch a n n e ls Each channel has independent oscillator, baud-rate generator, and PLL for clock recovery, dram atically reducing external com ponents.
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Z8030/Z8530
Z8030
Z8000
CRC-16
Z8530)
WF006011
ZBS30H*
Z8530
8080a intel microprocessor Architecture Diagram
ABOTT
microprocessor 80286
AM7960
SDLC scc pll
TTPC
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Untitled
Abstract: No abstract text available
Text: r z 7 S C S -T H O M S O N “ 7# li* « L iO T ô K S ' TDA0161 PROXIMITY DETECTORS • OUTPUT C U R R E N T: 10 mA ■ OSCILLATOR FREQUENCY : 10 MHz ■ SUPPLY VOLTAGE : + 4 TO + 35 V M IN ID IP/2 DESCRIPTION SO-8J TO-99 These monolithic integrated circuits are designed
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TDA0161
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Untitled
Abstract: No abstract text available
Text: DS21T11 PRODUCT PREVIEW DALLAS SEMICONDUCTOR DS21T11 SCSI Terminator FEATURES Fully com pliant Ultra SCSI PIN ASSIGNMENT with S C S I-1 , Fast SCSI and Provides active term ination for 18 signal lines 5% tolerance on term ination resistors and voltage regulator
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DS21T11
DS21T11
28-PIN
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D481850G
Abstract: t838 D481850
Text: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT ¿ P D 481850 f o r R e v . L 8 M-BIT SYNCHRONOUS GRAM 128K-WORD BY 32-BIT BY 2-BANK Description The /¿PD481850 is a synchronous graphics memory (SGRAM organized as 131,072 words x 32 bits x 2 banks random access port.
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128K-WORD
32-BIT
uPD481850
100-pin
D481850G
t838
D481850
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M51594afp
Abstract: No abstract text available
Text: MITSUBISHI SOUND PROCESSORS M51594AFP PICKUP SERVO CONTROL DESCRIPTION The M 51594A F P com pact disc is a sem iconductor players. It integrated circuit PIN CONFIGURATION TOP VIEW cryises o f amplifiers, sw itches, APC SW OUT [ T comparators and logic controller fo r servo control o f an
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M51594AFP
1594A
51598FP
51599FP
42-pin
M51594afp
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80486 microprocessor block diagram and pin diagram
Abstract: CY7C1324
Text: CYPRESS CY7C1324 3.3V 128K x 18 Synchronous Cache RAM Features Functional Description • S u p p o rts 117 -M H z m icro p ro c ess o r c a ch e s y ste m s w ith zero w ait states T he C Y 7 C 1 324 is a 3.3V, 128K by 18 synch ron ous cache RAM d e sig ned to interface w ith high-speed m icro proce ssors
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117-MHz
100-pin
CY7C1324
CY7C1324
80486 microprocessor block diagram and pin diagram
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Untitled
Abstract: No abstract text available
Text: fax id: 1080 CY7C1329 64K x 32 Synchronous-Pipelined Cache RAM Featu res Funct ional Description T h e C Y 7 C 1 329 is 3.3 V 64 K by 32 synch ron ous-p ip eline d cache SR AM designed to su p p o rt zero w a it state seco nd ary cache with m inim al glue logic.
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CY7C1329
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rtd 2660
Abstract: RPX 10 PLC programming GK transistor 72 SK 10 BAT 065 je350 transistor kl1 TRANSISTOR JE350 resistor 400ohm VOLTAGE LEVEL RELAY SJ 195
Text: /= T ^7 # I S G S -T H O M S O N KÆO [^@[l[L[l©Tr[^ Q [RDD©S L3037 SUBSCRIBER LINE INTERFACE CIRCUIT PRELIM IN ARY DATA I • ■ . . ■ . ■ ■ . ■ ■ ■ M O N O C H IP S ILIC O N SLIC S U IT A B LE FOR P U B LIC /P R IV A T E A P P LIC A T IO N S
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L3037
100ms)
L3037
rtd 2660
RPX 10 PLC programming
GK transistor 72
SK 10 BAT 065
je350 transistor
kl1 TRANSISTOR
JE350
resistor 400ohm
VOLTAGE LEVEL RELAY SJ 195
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Untitled
Abstract: No abstract text available
Text: Semiconductor Data Sheet October 1998 File Number 4129.3 10-Bit, 40 MSPS A/D Converter Features T he H I5746 is a m onolithic, 10-bit, an alog-to-d ig ital co n ve rte r fab ricated in a C M O S process. It is de sig ned for • S am pling R a t e .40 M SPS
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10-Bit,
HI5746
225mW
HI5702
HI5703.
HI5767
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P502C
Abstract: aish connector iso 2593 EIA-S30 SP502A
Text: Sipe* SP502 SIGNAL P R O C tS S IN C i fcXCFi I T N O t Multi-Mode Serial Transceiver Single-Chip Serial Transceiver Supports Industry-Standard Software-Selectable Protocols: — RS232 V.28 — RS422A (V.11, X.27) — RS449 — RS485 — V.35 — EIA-530
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SP502
RS232
RS422A
RS449
RS485
EIA-530
RS449,
P502C
aish
connector iso 2593
EIA-S30
SP502A
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Untitled
Abstract: No abstract text available
Text: MftS 2 2 FUJITSU M B86962 10BASE-T TRANSCEIVER FOR TWISTED PAIR ETHERNET FEBRUARY 1991 PRELIMINARY DATA SHEET face permits capacitive coupling to the external Manchester encoder/decoder, eliminating the isola tion coupling transformer usually required at that in
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B86962
10BASE-T
10BASE-T
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ET9421
Abstract: ET9420 N-Channel Microcontrollers gi 9420 ET9320 OPTION17
Text: O THOMSON SEMICONDUCTEURS ET9420/942179422 • ET9320/932179322 SINGLE-CHIP MICROCONTROLLERS T h e E T 9 4 2 0 / 9 4 2 1 /9 4 2 2 , E T 9 3 2 0 / 9 3 2 1 an d 9 3 2 2 Sin g le- C h ip NC h a n n e l M ic ro c o n tro lle rs are fu lly co m p atib le w ith th e C O P S
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ET9420/942179422
ET9320/932179322
ET9420/9421/9422,
ET9320/9321
ET9421
ET9420,
ET9420
28-pin
ET9421
24-pin
ET9420
N-Channel Microcontrollers
gi 9420
ET9320
OPTION17
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S037D
Abstract: No abstract text available
Text: TL7702B, TL7705B, TL7702BY, TL7705BY SUPPLY VOLTAGE SUPERVISORS SLVS037D - SEPTEMBER 1989 - REVISED AUGUST 1995 * P ow e r - O n R e s e t G e n e r a t o r TL77xxBC . . . P OR D P A C K A G E T L 7 7 x x B M . . . JG P A C K A G E * A ut o m a t i c R e s e t Ge n e r a t i o n After
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TL7702B,
TL7705B,
TL7702BY,
TL7705BY
SLVS037D
TL77xxBC
S037D
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opb 3902
Abstract: esis power ups RCA Solid State amplifier TETRA TETRA radio HT-200R RCA SOLID STATE sds ts2 TETRA monitoring audi mmi
Text: 3900 Series Digital Radio Test Set TETRA Option Manual 1002-4401-3P0 Issue-8 EXPORT CONTROL WARNING: This document contains controlled technology or technical data under the jurisdiction of the Export Administration Regulations EAR , 15 CFR 730-774. It cannot be transferred to any foreign
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1002-4401-3P0
syst91]
1002-4401-3P0*
opb 3902
esis power ups
RCA Solid State amplifier
TETRA
TETRA radio
HT-200R
RCA SOLID STATE
sds ts2
TETRA monitoring
audi mmi
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ats vd hen tv
Abstract: No abstract text available
Text: €SS ESS Technology, Inc. ES3301 A/V Transport Demultiplexer, Descrambler Product Brief O VERVIEW FEATURES The ES3301 is a versatile tran spo rt-la yer dem ultiplexer, parser, and d escram bler designed fo r Set-Top Box, DVD, and B roadcast PC applications. It is fu lly program m able
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ES3301
32-bit
ES3308,
SAM0080-020298
ats vd hen tv
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