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    A54SX32 Price and Stock

    Microchip Technology Inc A54SX32A-TQG100I

    IC FPGA 81 I/O 100TQFP
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    DigiKey A54SX32A-TQG100I Tray 176 1
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    Microchip Technology Inc A54SX32A-TQG100I 1,777
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    Microchip Technology Inc A54SX32A-2PQG208I

    IC FPGA 174 I/O 208QFP
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    DigiKey A54SX32A-2PQG208I Tray 48 1
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    Microchip Technology Inc A54SX32A-PQG208

    IC FPGA 174 I/O 208QFP
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    DigiKey A54SX32A-PQG208 Tray 40 1
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    Mouser Electronics A54SX32A-PQG208 17
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    Verical A54SX32A-PQG208 20 1
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    Microchip Technology Inc A54SX32A-PQG208 140
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    NAC A54SX32A-PQG208 Tray 24
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    Avnet Silica A54SX32A-PQG208 16 Weeks 24
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    Microchip Technology Inc A54SX32A-PQG208I

    IC FPGA 174 I/O 208QFP
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    DigiKey A54SX32A-PQG208I Tray 40 1
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    Avnet Americas A54SX32A-PQG208I Tray 48 12 Weeks 24
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    Mouser Electronics A54SX32A-PQG208I 13
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    Verical A54SX32A-PQG208I 24 1
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    A54SX32A-PQG208I 16 16
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    Microchip Technology Inc A54SX32A-1PQG208I

    IC FPGA 174 I/O 208QFP
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    DigiKey A54SX32A-1PQG208I Tray 30 1
    • 1 $306.06
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    Mouser Electronics A54SX32A-1PQG208I 24
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    Avnet Silica A54SX32A-1PQG208I 14 Weeks 24
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    A54SX32 Datasheets (500)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    A54SX32 Actel 54SX Family FPGAs Original PDF
    A54SX32-1 Actel 54SX Family FPGAs Original PDF
    A54SX32-1BCQ208 Actel FPGAs RadTolerant and HiRel Original PDF
    A54SX32-1BCQ256 Actel FPGAs RadTolerant and HiRel Original PDF
    A54SX32-1BG208 Actel 54SX Family FPGAs Original PDF
    A54SX32-1BG208I Actel 54SX Family FPGAs Original PDF
    A54SX32-1BG208M Actel 54SX Family FPGAs Original PDF
    A54SX32-1BG208PP Actel 54SX Family FPGAs Original PDF
    A54SX32-1BG313 Actel Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 249 I/O 313BGA Original PDF
    A54SX32-1BG313 Actel FPGA Original PDF
    A54SX32-1BG313 Actel SXA FPGA 32K System Gates Original PDF
    A54SX32-1BG313I Actel Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 249 I/O 313BGA Original PDF
    A54SX32-1BG313I Actel FPGA Original PDF
    A54SX32-1BG313I Actel SXA FPGA 32K System Gates Original PDF
    A54SX32-1BG313M Actel Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 249 I/O 313BGA Original PDF
    A54SX32-1BG313M Actel FPGA Original PDF
    A54SX32-1BG313M Actel SXA FPGA 32K System Gates Original PDF
    A54SX32-1BG329 Actel Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 249 I/O 329BGA Original PDF
    A54SX32-1BG329 Actel FPGA Original PDF
    A54SX32-1BG329 Actel SXA FPGA 32K System Gates Original PDF
    ...

    A54SX32 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    actel

    Abstract: A54SX32 54SX A54SX16
    Text: Errata v2.0 54SX Family FPGAs RadTolerant and HiRel Errata In Table 1 on page 8, the Maximum Input Tolerance for the A54SX16 and A54SX32 devices is incorrect. Here is how the table should appear. Table 1 • Supply Voltages Devices A54SX16 A54SX32 RT54SX16


    Original     		PDF A54SX16 A54SX32 A54SX16 A54SX32 RT54SX16 RT54SX32 5172141-7E/3 actel 54SX

    vhdl code for manchester decoder

    Abstract: manchester verilog decoder MIL-HDBK-1553A 1553b VHDL 1553b bu-63147 fpga 1553B SA30L Verilog implementation of a Manchester Encoder/Decoder
    Text: v3.0 MIL-STD-1553B Remote Terminal Core1553BRT Pr od uc t S um m ary De vel opm en t Sy s te m In t e n d e d U s e • Complete 1553BRT Implementation, Implemented in an A54SX32A • 1553B Remote Terminal RT • DMA Backend Interface to External Memory


    Original     		PDF MIL-STD-1553B Core1553BRT 1553B 1553BRT A54SX32A 1553B vhdl code for manchester decoder manchester verilog decoder MIL-HDBK-1553A 1553b VHDL bu-63147 fpga 1553B SA30L Verilog implementation of a Manchester Encoder/Decoder

    actel cqfp 84

    Abstract: A1010B ACTEL FBGA 144
    Text: v3.0 Package Options: User I/Os per Package C om m e r c i a l / I nd us t r i a l D ev i c e s A54SX16 A54SX16P A54SX32 130 175 175 174 81 81 81 A54SX08 A54SX72A SX A54SX32A A54SX16A 44 A54SX08A PLCC SX-A eX256 Pins eX128 Package eX64 eX 68 84 PQFP 69 100


    Original     		PDF A54SX08A A54SX16A A54SX32A A54SX72A A54SX08 A54SX16 A54SX16P A54SX32 eX128 eX256 actel cqfp 84 A1010B ACTEL FBGA 144

    54SX32

    Abstract: A54SX32 A54SX32A A54SX72A PAR64 REQ64 54SX32A il 074
    Text: Preliminary v1.0 HiRel SX-A Family FPGAs Le a di n g E d ge P er f o r m a n ce • QML Certified Devices • 215 MHz System Performance Military Temperature • 100% Military Temperature Tested (–55°C and +125°C) • 5.3ns Clock-to-Out (Pin-to-Pin) (Military Temperature)


    Original     		PDF

    10uH inductor CC TECHNOLOGIES

    Abstract: APA150 -TQ1001 datasheet AX2000 ISL6528 HSOP-28 thermal Actel APA075 ax rubycon capacitor 106 35K 7 pin str for 24v 3 amp to 220 package APA600
    Text: HIGH PERFORMANCE ANALOG Power Management Application Guide for Actel FPGAs Using Switchers to Power Actel FPGAs FPGAs continue to grow in density and complexity while at the same time, shrinking device geometries have enabled faster system clocks and required lower core voltages. These trends call for more


    Original     		PDF

    1553b VHDL

    Abstract: Actel 1553b fpga 1553B transistor BC 584 MIL-STD-1553B FPGA RT MIL-STD-1553B ACTEL FPGA manchester verilog decoder vhdl code manchester encoder mil-std-1553b SPECIFICATION transistor BC 490
    Text: Core1553BBC MIL-STD-1553B Bus Controller Product Summary • Intended Use • 1553B Bus Controller BC • DMA Backend Interface to External Memory Synthesis and Simulation Support Key Features • • • • • • Supports MIL-STD-1553B Interfaces to External RAM


    Original     		PDF Core1553BBC MIL-STD-1553B 1553B MIL-STD-1553B 128kbytes Core1553BRT 1553b VHDL Actel 1553b fpga 1553B transistor BC 584 MIL-STD-1553B FPGA RT MIL-STD-1553B ACTEL FPGA manchester verilog decoder vhdl code manchester encoder mil-std-1553b SPECIFICATION transistor BC 490

    HiRel a54sx72a unused

    Abstract: No abstract text available
    Text: Advanced v1.3 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LET th > 40, GEO SEU Rate < 10–10


    Original     		PDF RT54SX-S RT54SX-S TM1019 HiRel a54sx72a unused

    rt54sx32su

    Abstract: RTSX72 RTSX32SU RTSX72-S
    Text: Advanced v0.1 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case


    Original     		PDF TM1019 rt54sx32su RTSX72 RTSX32SU RTSX72-S

    Pin Compatibility Allows Prototyping with Commercial SX-A FPGAs

    Abstract: RT54SX72S-CQ256 RTSX32S
    Text: Advanced v 0.1.1 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 Additional SEU Hardened Flip-Flops Eliminate Software TMR Necessity LETth > 40, GEO SEU Rate <


    Original     		PDF RT54SX-S 100krad RT54SX-S Pin Compatibility Allows Prototyping with Commercial SX-A FPGAs RT54SX72S-CQ256 RTSX32S

    Untitled

    Abstract: No abstract text available
    Text: v2 . 1 RTSX-S RadTolerant FPGAs Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case


    Original     		PDF TM1019

    Untitled

    Abstract: No abstract text available
    Text: v3.2 SX Family FPGAs u e Leading Edge Performance • • • • Features 320 MHz Internal Performance 3.7 ns Clock-to-Out Pin-to-Pin 0.1 ns Input Setup 0.25 ns Clock Skew • • • • • • • • Specifications • • • • 12,000 to 48,000 System Gates


    Original     		PDF

    CQFP 256 PIN actel

    Abstract: No abstract text available
    Text: Pr el i mi nar y v 1. 3 54SX Family FPGAs RadTolerant and HiRel Features • 100% Resource Utilization with 100% Pin Locking RadTolerant 54SX Family • Mixed Voltage Support—3.3V Operation with 5.0V Input Tolerance • Tested Total Ionizing Dose TID Survivability Level


    Original     		PDF

    sx08a

    Abstract: No abstract text available
    Text: v4.0  SX-A Family FPGAs u e Le a di n g- E d ge P er f o r m a n ce • Configurable I/O Support for 3.3V/5V PCI, 5V TTL, 3.3V LVTTL, 2.5V LVCMOS2 • 2.5V, 3.3V, and 5V Mixed-Voltage Operation with 5V Input Tolerance and 5V Drive Strength • Devices Support Multiple Temperature Grades


    Original     		PDF

    TM101

    Abstract: No abstract text available
    Text: Advanced v1.2.3 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LETth > 40, GEO SEU Rate < 10–10


    Original     		PDF RT54SX-S 100krad RT54SX-S TM1019 TM101

    A54SX16A

    Abstract: No abstract text available
    Text: v4.0  SX-A Family FPGAs u e Le a di n g- E d ge P er f o r m a n ce • Configurable I/O Support for 3.3V/5V PCI, 5V TTL, 3.3V LVTTL, 2.5V LVCMOS2 • 2.5V, 3.3V, and 5V Mixed-Voltage Operation with 5V Input Tolerance and 5V Drive Strength • Devices Support Multiple Temperature Grades


    Original     		PDF

    HiRel a54sx72a unused

    Abstract: No abstract text available
    Text: Advanced v1.6 RTSX-S RadTolerant FPGAs for Space Application S p ec i a l F e a tu r es fo r S p ac e • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LET th > 40, GEO SEU Rate < 10–10


    Original     		PDF TM1019 HiRel a54sx72a unused

    RTSX32su

    Abstract: RTSX32SU CQ84 RTSX72SU
    Text: v2.0 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case


    Original     		PDF TM1019 RTSX32su RTSX32SU CQ84 RTSX72SU

    vhdl code for motor speed control

    Abstract: ANTIFUSE
    Text: Actel’s Antifuse FPGAs Programmable ASIC Solutions Space Electronics Communications Infrastructure e-Appliances The Antifuse Advantage Actel’s antifuse devices are low-cost, high-performance solutions for today’s logic designer. Ideal for integrating logic typically implemented in multiple CPLDs, PALs,


    Original     		PDF

    actel a1240

    Abstract: Signal path designer 176-CPGA Actel a1280 pinout
    Text: Designer User’s Guide Windows ® and UNIX® Environments Actel Corporation, Sunnyvale, CA 94086 2000 Actel Corporation. All rights reserved. Printed in the United States of America Part Number: 5029122-0 Release: July 2000 No part of this document may be copied or reproduced in any form or by


    Original     		PDF

    Untitled

    Abstract: No abstract text available
    Text: Advanced v0.1.1 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 Additional SEU Hardened Flip-Flops Eliminate Software TMR Necessity LETth > 40, GEO SEU Rate <


    Original     		PDF RT54SX-S 100krad

    Untitled

    Abstract: No abstract text available
    Text: v3.0 SX-A Family FPGAs Leading-Edge P erfo rm an c e • 250 MHz System Performance • 3.8ns Clock-to-Out Pad-to-Pad • 350 MHz Internal Performance S p ec ific atio n s • • • • 12,000 to 108,000 Available System Gates Up to 360 User-Programmable I/O Pins


    OCR Scan     		PDF 22p/0

    54sx08

    Abstract: THERMAL Fuse m20 tf 115 c
    Text: v 3 .0 54SX Family FPGAs Leading Edge Performance • 100%Resource Utilization with 100%Pin Locking • 320 MHz Internal Performance • 3.3VOperation with 5.0VInput Tolerance • 3.7 nsClock-to-Out Pi n-to-Pi n • Very Low Power Consumption • 0.1 ns Input Set-Up


    OCR Scan     		PDF

    Untitled

    Abstract: No abstract text available
    Text: 54SXFamily FPGAs Leadi ng Edge P e r f o r m a nc e • • 320 MHz Internal Performance • 3.3VOperation with 5.0YInput Tolerance • 3.7 ns Qock-to-Out Pin-to-Pin • • 0.1ns Input Set-Up • Deterministic, Ufcer-Controllable Timing • 0.25 ns d o c k Skew


    OCR Scan     		PDF 54SXFamily

    ACTEL BGA329

    Abstract: LRD12 54SX A54SX08 A54SX16 A54SX32 PAR64 REQ64 LRD-12 A54SX16P PQFP
    Text: -m e te f v 3 .0 - m 54SX Fami ly FPGAs Leadi ng Edge P e r f o r m a n c e • • 320 MHz Internal Performance • 3.3VOperation with 5.0YInput Tolerance • 3.7 ns Qock-toOut Pin-to-Pin • \fcry Low Power Consumption


    OCR Scan     		PDF PBGA313 PBGA329 ACTEL BGA329 LRD12 54SX A54SX08 A54SX16 A54SX32 PAR64 REQ64 LRD-12 A54SX16P PQFP