Untitled
Abstract: No abstract text available
Text: 54SXFamily FPGAs Leadi ng Edge P e r f o r m a nc e • • 320 MHz Internal Performance • 3.3VOperation with 5.0YInput Tolerance • 3.7 ns Qock-to-Out Pin-to-Pin • • 0.1ns Input Set-Up • Deterministic, Ufcer-Controllable Timing • 0.25 ns d o c k Skew
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54SXFamily
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Untitled
Abstract: No abstract text available
Text: P r e l i m i n a r y v 1 .3 54SXFamily FPGAs RadTolerant and HiRcl Features • 100%Resource Utilization with 100%Pin Locking R a d T o l e r a n t 5 4 S X F am i l y • Mxed Voltage Support— 3.3VOperation with 5.0VInput Tolerance • Tested Total IonizingDose TID Survivability Level
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54SXFamily
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Untitled
Abstract: No abstract text available
Text: W ie te l Preüminary - m v1 . 2 54SXFamily FPGAs RadTolerant and HiRcl Features • 100%Resource Utilization with 100%Pin Locking R a d T o l e r a n t 5 4 S X F am i l y • Mxed Voltage Support— 3.3VOperation with 5.0VInput
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54SXFamily
CQ208
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ACTEL BGA329
Abstract: LRD12 54SX A54SX08 A54SX16 A54SX32 PAR64 REQ64 LRD-12 A54SX16P PQFP
Text: -m e te f v 3 .0 - m 54SX Fami ly FPGAs Leadi ng Edge P e r f o r m a n c e • • 320 MHz Internal Performance • 3.3VOperation with 5.0YInput Tolerance • 3.7 ns Qock-toOut Pin-to-Pin • \fcry Low Power Consumption
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PBGA313
PBGA329
ACTEL BGA329
LRD12
54SX
A54SX08
A54SX16
A54SX32
PAR64
REQ64
LRD-12
A54SX16P PQFP
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