actel cqfp 84
Abstract: A1010B ACTEL FBGA 144
Text: v3.0 Package Options: User I/Os per Package C om m e r c i a l / I nd us t r i a l D ev i c e s A54SX16 A54SX16P A54SX32 130 175 175 174 81 81 81 A54SX08 A54SX72A SX A54SX32A A54SX16A 44 A54SX08A PLCC SX-A eX256 Pins eX128 Package eX64 eX 68 84 PQFP 69 100
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A54SX08A
A54SX16A
A54SX32A
A54SX72A
A54SX08
A54SX16
A54SX16P
A54SX32
eX128
eX256
actel cqfp 84
A1010B
ACTEL FBGA 144
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Untitled
Abstract: No abstract text available
Text: v3.2 SX Family FPGAs u e Leading Edge Performance • • • • Features 320 MHz Internal Performance 3.7 ns Clock-to-Out Pin-to-Pin 0.1 ns Input Setup 0.25 ns Clock Skew • • • • • • • • Specifications • • • • 12,000 to 48,000 System Gates
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a54sx72a
Abstract: TQFP-176 footprint A54SX16A A54SX32A-
Text: Application Note SX to SX-A Design Migration I n tro du ct i on • Configurable Output State During Power Up: All outputs can be programmed to either weak resistor pull up or weak resistor pull down for output tristate. SX-A is fabricated using a 0.22/0.25µ CMOS process. These
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A54SX16A
Abstract: A54SX72A A54SX08A A54SX32 A54SX32A AC157 PQ208 A54SX08 A54SX16 A54SX16P PQFP
Text: Application Note AC157 SX to SX-A Design Migration I n tro du ct i on • Configurable Output State During Power Up: All outputs can be programmed to either weak resistor pull up or weak resistor pull down for output tristate. SX-A is fabricated using a 0.22/0.25µ CMOS process. These
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AC157
A54SX16A
A54SX72A
A54SX08A
A54SX32
A54SX32A
AC157
PQ208
A54SX08
A54SX16
A54SX16P PQFP
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THERMAL Fuse m20 tf 115 c
Abstract: SX v3.1 REQ64 A54SX08 A54SX16 A54SX32 PAR64 313 pin PBGA fq1200 THERMAL Fuse l20 tf 115 c
Text: v3.2 SX Family FPGAs u e Leading Edge Performance • • • • Features 320 MHz Internal Performance 3.7 ns Clock-to-Out Pin-to-Pin 0.1 ns Input Setup 0.25 ns Clock Skew • • • • • • • • Specifications • • • • 12,000 to 48,000 System Gates
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THERMAL Fuse m20 tf 115 c
Abstract: 54SX A54SX08 A54SX16 A54SX32 PAR64 REQ64 circuit diagram of motherboard W2-081 ac 171
Text: v3.1 54SX Family FPGAs Le a di ng E dg e P er f or m a nc e F ea t u r es • 320 MHz Internal Performance • 66 MHz PCI • 3.7 ns Clock-to-Out Pin-to-Pin • CPLD and FPGA Integration • 0.1 ns Input Set-Up • Single Chip Solution • 0.25 ns Clock Skew
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54SX
Abstract: A54SX08 A54SX16 A54SX32 PAR64 REQ64 38VCC 54SX16P
Text: v3.0.1 54SX Family FPGAs Lead ing E dge P er f or m ance Feat ur es • 320 MHz Internal Performance • 66 MHz PCI • 3.7 ns Clock-to-Out Pin-to-Pin • CPLD and FPGA Integration • 0.1 ns Input Set-Up • Single Chip Solution • 0.25 ns Clock Skew • 100% Resource Utilization with 100% Pin Locking
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sx 2082
Abstract: No abstract text available
Text: v3.0 54SX Family FPGAs Lead ing E dge P er f or m ance Feat ur es • 320 MHz Internal Performance • 66 MHz PCI • 3.7 ns Clock-to-Out Pin-to-Pin • CPLD and FPGA Integration • 0.1 ns Input Set-Up • Single Chip Solution • 0.25 ns Clock Skew • 100% Resource Utilization with 100% Pin Locking
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A40MX04
Abstract: ACTEL FBGA 144 A42MX09 A42MX24 A42MX16
Text: Actel FPGA Selector Guide Commercial & Industrial Devices eX SX-A SX MX ProASIC System Typical Gates Gates Logic Dedicated Max Modules Flip-Flops Flip-Flops SRAM Max I/O 2.5V CMOS 3.3V CMOS 5V CMOS 5V Tolerant 3.3V 5V Slew Rate Routed Hardwired Bits Available
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eX128
eX256
A40MX04
ACTEL FBGA 144
A42MX09
A42MX24
A42MX16
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A500K180
Abstract: A42MX16 ACTEL FBGA 144 A42MX09
Text: Actel FPGA Selector Guide Commercial & Industrial Devices SX-A SX MX ProASIC System Typical Gates Gates Logic Dedicated Max SRAM Max I/O 2.5V CMOS 3.3V CMOS 5V CMOS 5V Tolerant 3.3V 5V Slew Rate Routed Hardwired 33 MHz 66 MHz Temp Speed Bits Available drive
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A54SX08A
A54SX16A
A54SX32A
A54SX72A
A500K180
A42MX16
ACTEL FBGA 144
A42MX09
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PMX32
Abstract: pqfp 3.2mm footprint a54sx72a
Text: Actel FPGA Selector Guide System Gates Typical Gates Logic Modules Dedicated FlipFlops Max FlipsFlops SRAM Bits Max I/O Available 2.5V CMOS Drive 3.3V CMOS Drive 5V CMOS Drive 5V Tolerant Inputs 3.3V PCI I/O 5V PCI I/O Slew Rate Control Routed Clocks HardWired
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FG1152
APA075
APA150
APA300
APA450
APA600
APA750
APA1000
AX125
AX250
PMX32
pqfp 3.2mm footprint
a54sx72a
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actel cqfp 84
Abstract: actel a1020b RT1425A actel a1010b actel 172 cqfp
Text: Package Options: User I/Os per Package January 1999 1999 Actel Corporation 1 Commercial/Industrial Devices RQFP VQFP TQFP BGA CPGA CQFP 129 172 172 125 176 34 57 69 69 72 83 72 72 57 125 125 152 125 176 176 202 176 176 202 57 78 112 129 78 144 78 112 144
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A54SX16P
A42MX09
A54SX08
A54SX16
A54SX32
A42MX16
A42MX24
A42MX36
A32100DX
A40MX02
actel cqfp 84
actel a1020b
RT1425A
actel a1010b
actel 172 cqfp
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FBGA-484
Abstract: FBGA484 ACTEL FBGA 144
Text: Actel FPGA Selector Guide Ava i l a b l e Co m m e rc i a l & In d u s t r i a l De v i c e s 54SX-A 54SX 40MX 42MX ProASIC System Typical Gates Gates Logic Max SRAM Max I/O 2.5V CMOS 3.3V CMOS 5V CMOS 5V Tolerant 3.3V 5V Slew Rate Flip Flops Bits Available
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33MHz
66MHz
54SX-A
SX08A
SX16A
SX32A
SX72A
FBGA-484
FBGA484
ACTEL FBGA 144
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QFN108
Abstract: QFN-132 kl1-v1 208 pin rqfp drawing qfn132 RT3PE3000L CQ256 DIMENSIONS pqfp 100 actel package mechanical drawing Actel A40MX04 PBGA 23X23 0.8 pitch
Text: v 11. 2 Package Mechanical Drawings Ceramic Pin Grid Array 84-Pin CPGA Top View 0.050" ± 0.010" Pin #1 ID 0.045" 0.055" 0.015" 0.018" ± 0.002" 0.100" BSC 1.100" ± 0.020" square 0.072" 0.088" L 0.120" 0.140" Side View K J H G F 1.000" BSC E D C B A 1 2 3
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84-Pin
A1010B
A1020B
100-Pin
QFN108
QFN-132
kl1-v1
208 pin rqfp drawing
qfn132
RT3PE3000L CQ256
DIMENSIONS pqfp 100
actel package mechanical drawing
Actel A40MX04
PBGA 23X23 0.8 pitch
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54sx08
Abstract: THERMAL Fuse m20 tf 115 c
Text: v 3 .0 54SX Family FPGAs Leading Edge Performance • 100%Resource Utilization with 100%Pin Locking • 320 MHz Internal Performance • 3.3VOperation with 5.0VInput Tolerance • 3.7 nsClock-to-Out Pi n-to-Pi n • Very Low Power Consumption • 0.1 ns Input Set-Up
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Untitled
Abstract: No abstract text available
Text: 54SXFamily FPGAs Leadi ng Edge P e r f o r m a nc e • • 320 MHz Internal Performance • 3.3VOperation with 5.0YInput Tolerance • 3.7 ns Qock-to-Out Pin-to-Pin • • 0.1ns Input Set-Up • Deterministic, Ufcer-Controllable Timing • 0.25 ns d o c k Skew
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54SXFamily
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ACTEL BGA329
Abstract: LRD12 54SX A54SX08 A54SX16 A54SX32 PAR64 REQ64 LRD-12 A54SX16P PQFP
Text: -m e te f v 3 .0 - m 54SX Fami ly FPGAs Leadi ng Edge P e r f o r m a n c e • • 320 MHz Internal Performance • 3.3VOperation with 5.0YInput Tolerance • 3.7 ns Qock-toOut Pin-to-Pin • \fcry Low Power Consumption
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PBGA313
PBGA329
ACTEL BGA329
LRD12
54SX
A54SX08
A54SX16
A54SX32
PAR64
REQ64
LRD-12
A54SX16P PQFP
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k16 a21
Abstract: 313-pin
Text: ^ c M J P relim inary • v 1 .1 54SX Family FPGAs Features • 3.3VOperation with 5.0VInput Tolerance Hi gh P e r f o r m ance • Low Power Consumption • 320 MHz Internal Performance • Deterministic, User-ControlIableTiming • 4.0 nsClock-to-Out Pi n-to-Pi n
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THERMAL Fuse m20 tf 115 c
Abstract: 54SX16A actel fpga 54sx32 54SX32
Text: ^ c te l v 2 .0 54SX Family FPGAs L ea d in g Edge Pe rform an ce • 100% Resource Utilization with 100%Pin Locking • 320 MHz Internal Performance • 3.3V Operation with 5.0V Input Tolerance • 3.7 ns Clock-to-Out Pm-to-Pin • Very Low Power Consumption
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AS4SX32
THERMAL Fuse m20 tf 115 c
54SX16A
actel fpga 54sx32
54SX32
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b23n20
Abstract: No abstract text available
Text: ^ c te -m v 2. 0 l 54SX Family FPGAs • • • • • 100%Resource Utilization with 100%Pin Locking 3.3VOperation with 5.0VInput Tolerance Very Low Power Consumption Deterministic, User-ControlIableTiming Unique, In-System Diagnostic and Debug capability with
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0001o
A54SX08
PBGA313
PBGA329
b23n20
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LRD12
Abstract: IRD12
Text: 54SX Family FPGAs Features • 3.3VOperation with 5.0VInput Tolerance High • Low Power Consumption Perform ance • 320 MHz I nternal Performance • Deterministic, User-ControlIableTiming • 4.0 ns Cl ock-to-Out Pin-to-Pin • Unique, In-System Diagnostic and Debug Facility with
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0001o
MO-151
LRD12
IRD12
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Untitled
Abstract: No abstract text available
Text: P r e l i m i n a r y v 1 .3 54SXFamily FPGAs RadTolerant and HiRcl Features • 100%Resource Utilization with 100%Pin Locking R a d T o l e r a n t 5 4 S X F am i l y • Mxed Voltage Support— 3.3VOperation with 5.0VInput Tolerance • Tested Total IonizingDose TID Survivability Level
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54SXFamily
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Untitled
Abstract: No abstract text available
Text: 54SX Family FPGAs RadTolerant and HiRel Features R a d T ole ran t 54SX Family • • • • • TestedTotal Ionizing Dose TID Survivability Level Devices Avail able from Tested Lots Radiation Performance to 100K Rads Up to 160 MHz On-Chip Performance
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CQ208
CQ256
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Untitled
Abstract: No abstract text available
Text: Preliminary v 1 .2 54SX Family FPGAs RadTolerant and HiRel Features • 100%Resource Utilization with 100%Pin Locking Rad T o lera nt 54SX Family • Mixed Voltage Support— 3.3V Operation with 5.0V Input • TestedTotal Ionizing Dose TID Survivability Level
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