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    HSP50214A Price and Stock

    Rochester Electronics LLC HSP50214AVC

    PROGRAMMABLE DOWNCONVERTER
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    DigiKey HSP50214AVC Bulk 9
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    Harris Semiconductor HSP50214AVC

    PROGRAMMABLE DOWNCONVERTER '
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    Rochester Electronics HSP50214AVC 2,799 1
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    HSP50214A Datasheets (3)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    HSP50214A Intersil Programmable Downconverter Original PDF
    HSP50214AVC Intersil Programmable Downconverter Original PDF
    HSP50214AVI Intersil Programmable Downconverter Original PDF

    HSP50214A Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    96330

    Abstract: No abstract text available
    Text: HSP50214A S E M I C O N D U C T O R Programmable Downconverter February 1998 Features Description • Up to 65 MSPS Front-End Processing Rates CLKIN and 55 MSPS (41 MSPS Using the Discriminator) Back-End Processing Rates (PROCCLK) Clocks May Be Asynchronous


    Original
    PDF HSP50214A HSP50214A 14-bit 255-RL 96330

    16 AS 15 HB1

    Abstract: No abstract text available
    Text: Calculating Maximum Processing Rates of the PDC HSP50214, HSP50214A and HSP50214B Application Note January 1999 AN9720.2 Authors: John Henkelman and Dave Damerow Introduction [ /Title (AN97 20) /Subject (Calculating Maximum Processing Rates of the PDC (HSP5


    Original
    PDF HSP50214, HSP50214A HSP50214B) AN9720 HSP50 16 AS 15 HB1

    cic filter

    Abstract: decimation filters HSP50214 logic diagram of ic 7432 DC variable power center tap HB2-0 HSP50214A HSP50214B
    Text: Calculating Maximum Processing Rates of the PDC HSP50214, HSP50214A and HSP50214B Application Note Introduction January 1999 AN9720.2 BAND OF INTEREST Configuring the Programmable Digital Downconverter (PDC) requires selecting clock, decimation and interpolation rates for


    Original
    PDF HSP50214, HSP50214A HSP50214B) AN9720 cic filter decimation filters HSP50214 logic diagram of ic 7432 DC variable power center tap HB2-0 HSP50214B

    cic filter

    Abstract: HSP50214 HSP50214A HSP50214B cic filter for digital down converter
    Text: TM Calculating Maximum Processing Rates of the PDC HSP50214, HSP50214A and HSP50214B Application Note January 1999 Introduction AN9720.2 BAND OF INTEREST Configuring the Programmable Digital Downconverter (PDC) requires selecting clock, decimation and interpolation rates for


    Original
    PDF HSP50214, HSP50214A HSP50214B) AN9720 cic filter HSP50214 HSP50214B cic filter for digital down converter

    cic filter

    Abstract: HSP50214 HSP50214A HSP50214B ASSP29 circuit diagram for FIR filter
    Text: Calculating Maximum Processing Rates of the PDC HSP50214, HSP50214A and HSP50214B Application Note January 1999 AN9720.2 Authors: John Henkelman and Dave Damerow Introduction BAND OF INTEREST Configuring the Programmable Digital Downconverter (PDC) requires selecting clock, decimation and interpolation rates for


    Original
    PDF HSP50214, HSP50214A HSP50214B) AN9720 cic filter HSP50214 HSP50214B ASSP29 circuit diagram for FIR filter

    Untitled

    Abstract: No abstract text available
    Text: Harris Semiconductor No. AN9720.1 Digital Signal Processing February 1998 Calculating Maximum Processing Rates of the PDC HSP50214, HSP50214A and HSP50214B Authors: John Henkelman and Dave Damerow Introduction greater than the maximum sample rate of the A/D or PDC, then


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    PDF AN9720 HSP50214, HSP50214A HSP50214B) 1-800-4-HARRIS

    CIC interpolation Filter

    Abstract: HSP50214 HSP50214A HSP50214B TB349 cic filter
    Text: Calculating the Maximum Output Sample Rate and Bandwidth Specifications of the HSP50214 TM Technical Brief January 1998 TB349.1 Authors: John Henkelman and David Damerow Output Sample Rate and Bandwidth Specifications Calculating the Output Rate • Output Samples at 6.6 MSPS with Output Bandwidths


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    PDF HSP50214 TB349 500kHz 625kHz HSP50214 982kHz HSP50214A CIC interpolation Filter HSP50214B cic filter

    AN9315

    Abstract: No abstract text available
    Text: Signal Processing Communications 3 Communications Products PAGE High Speed Converters HI1177 8-Bit, 40MSPS, 2-Channel D/A Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 HI5628 8-Bit, 165/125/60MSPS, Dual High Speed CMOS D/A Converter . . . . . . . . . . . . . . . . . . . . . . . .


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    PDF HI1177 HI5628 HI5640 HI5660 HI5662 HI5667 HI5721 HI5728 HI5731 HI5741 AN9315

    HSP50214

    Abstract: HSP50214A HSP50214B TB349 cic filter
    Text: Calculating the Maximum Output Sample Rate and Bandwidth Specifications of the HSP50214 Technical Brief January 1998 TB349.1 Authors: John Henkelman and David Damerow Output Sample Rate and Bandwidth Specifications • Output Samples at 6.6 MSPS with Output Bandwidths to


    Original
    PDF HSP50214 TB349 500kHz 625kHz HSP50214 982kHz HSP50214A HSP50214B cic filter

    Untitled

    Abstract: No abstract text available
    Text: Harris Semiconductor No. TB349.1 Digital Signal Processing January 1998 Calculating the Maximum Output Sample Rate and Bandwidth Specifications of the HSP50214 Authors: John Henkelman and David Damerow Output Sample Rate and Bandwidth Specifications Calculating the Output Rate


    Original
    PDF TB349 HSP50214 500kHz 625kHz HSP50214 982kHz HSP50214A HSP50214B 857MHz)

    Untitled

    Abstract: No abstract text available
    Text: Calculating the Maximum Output Sample Rate and Bandwidth Specifications of the HSP50214 Technical Brief January 1998 TB349.1 Authors: John Henkelman and David Damerow Output Sample Rate and Bandwidth Specifications • Output Samples at 6.6 MSPS with Output Bandwidths to


    Original
    PDF HSP50214 TB349 500kHz 35MHz/17 059MHz 28MHz/17 647MHz; 55MHz/17 235MHz) FO-006

    bpsk modulator 20mhz

    Abstract: Frequency Discriminator NMT-900 Numerically Controlled Oscillator tag c3 625 800 HSP50210 HSP50214A HSP50214AVC HSP50214AVI C 5021 F-R
    Text: CT ODU ODUCT R P PR TE OLE UTE OBS UBSTIT 4B LE S SP5021 H SSIB December 1999 Programmable Downconverter PO Features Description • Up to 65 MSPS Front-End Processing Rates CLKIN and 55 MSPS (41 MSPS Using the Discriminator) Back-End Processing Rates (PROCCLK)


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    PDF 100dB 255-Tap 982kHz 32-Bit bpsk modulator 20mhz Frequency Discriminator NMT-900 Numerically Controlled Oscillator tag c3 625 800 HSP50210 HSP50214A HSP50214AVC HSP50214AVI C 5021 F-R

    Untitled

    Abstract: No abstract text available
    Text: fÇjHARRIS HSP50214A S E M I C O N D U C T O R Programmable Downconverter February 1998 Features Description • Up to 65 MSPS Front-End Processing Rates CLKIN and 55 MSPS (41 MSPS Using the Discriminator) Back-End Processing Rates (PROCCLK) Clocks May Be Asynchronous


    OCR Scan
    PDF HSP50214A HSP50214A 14-bit 40MHz 28MHz 500kHz 500kHz.

    12S14

    Abstract: No abstract text available
    Text: H A R R IS Sem iconductor Calculating Maximum Processing Rates of the PDC HSP50214, HSP50214A and HSP50214B A p p lic a tio n N o te J a n u a ry 1999 Authors: John Henkelman and Dave Damerow Introduction BAND OF INTEREST Configuring the Programmable Digital Downconverter (PDC)


    OCR Scan
    PDF HSP50214, HSP50214A HSP50214B) HSP50214 ASSP-29 FO-006 12S14

    an-9744

    Abstract: Transistor 3-347 AN9726 AN9718 Transistor 3-354
    Text: H A Semiconductor RM S S Signal Processing Communications 3 C o m m u n ic a tio n s P ro d u cts PAGE HI1177 8-Bit, 40MSPS, 2-Channel D/A Converter. 3-5 HI5628 8-Bit, 165/125/60MSPS, Dual High Speed CMOS D/A Converter.


    OCR Scan
    PDF HI1177 HI5628 HI5640 HI5660 HI5662 HI5667 HI5721 HI5728 HI5731 HI5741 an-9744 Transistor 3-347 AN9726 AN9718 Transistor 3-354

    Untitled

    Abstract: No abstract text available
    Text: i ? i? ic Sem iconductor | Calculating the Maximum Output Sample Rate and Bandwidth Specifications of the HSP50214 T e c h n ic a l B n e l J a n u a ry 1998 TB 349.1 Authors: John Henkelman and David Damerow Output Sample Rate and Bandwidth Specifications


    OCR Scan
    PDF HSP50214 500kHz 625kHz HSP50214 982kHz HSP50214A HSP50214B 55MHz 857MHz