HCT10 Search Results

HC10

Abstract: CD54HC10 CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HC10E CD74HCT10 HCT10
Contextual Info: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54HC10, CD74HC10, HCT10, HCT10

CD74HCT107

Abstract: CD54HC107F3A CD54HCT107F3A CD74HC107E HC107 HCT10
Contextual Info: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54/74HC107, CD54/HCT107 Data sheet acquired from Harris Semiconductor SCHS139B Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised December 2002

HC-107

Abstract: HC107
Contextual Info: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54/74HC107, CD54/HCT107 Data sheet acquired from Harris Semiconductor SCHS139A Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised May 2000 Features

KK74AC109

Abstract: KK74AC109D KK74AC109N
Contextual Info: TECHNICAL DATA KK74AC109 Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS The KK74AC109 is identical in pinout to the LS/ALS109,HC/HCT109. The device inputs are compatible with standard CMOS outputs, with pullup resistors, they are compatible with LS/ALS outputs.

HC107

Abstract: 74HCT 74LS CD74HC107 CD74HC107E CD74HCT107 CD74HCT107E HCT10
Contextual Info: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD74HC107, HCT107 Data sheet acquired from Harris Semiconductor SCHS139 Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 Features Description • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times

Contextual Info: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54HC10, CD74HC10, HCT10, HCT10

HCT10

Abstract: CD54HC10 CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HC10E CD74HCT10 HC10
Contextual Info: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54HC10, CD74HC10, HCT10, HCT10

Contextual Info: 74HC/HCT107 flip-flops D U A L JK FLIP-F LO P W ITH R E SE T ; N E G A T IV E -E D G E T R IG G E R FEATURES T Y P IC A L • Output capability: standard • I q q category: flip-flops SYM BO L T h e reset {n R is an asy n ch ron ou s active L O W input. W hen L O W , it overrides the

CD54HC107

Abstract: CD54HC107F3A CD74HC107 CD74HC107E CD74HC107M CD74HCT107 HC107 HCT10
Contextual Info: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54HC107, CD74HC107, HCT107 Data sheet acquired from Harris Semiconductor SCHS139D Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised October 2003

CD54HC10

Abstract: CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HC10E CD74HCT10 HC10 HCT10
Contextual Info: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54HC10, CD74HC10, HCT10, HCT10

Contextual Info: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54HC107, CD74HC107, HCT107 Data sheet acquired from Harris Semiconductor SCHS139D Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised October 2003

IN74ACT109D

Abstract: IN74ACT109N
Contextual Info: IN74ACT109 DUAL J-K FLIP-FLOP WITH SET AND RESET High-Speed Silicon-Gate CMOS • • • • The IN74ACT109 is identical in pinout to the LS/ALS109, HC/HCT109. The IN74ACT109 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs.

HC-86

Abstract: HC09 hcoo HC07 hc86 hc132 HC123A HC-107 HC251 HC4050
Contextual Info: SELECTION GUIDE FUNCTION GATE BUFFER FLIP-FLOP STANDARD CODE NAND HCOO, HCTOO, HC03, HC10, HCT10, HC20, HC30, HC133, HCT30 NOR HC02, HCT02, HC27, HCT27, HC4002, HC4078 AND HC08, HCT08, HC09, HC11, HC21 OR HC32, HCT32, HC4072, HC4075 EX NOR HC266, HC7266 EX OR

IN74AC109

Abstract: IN74AC109D IN74AC109N
Contextual Info: TECHNICAL DATA IN74AC109 Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS The IN74AC109 is identical in pinout to the LS/ALS109,HC/HCT109. The device inputs are compatible with standard CMOS outputs, with pullup resistors, they are compatible

IN74AC10N

Abstract: IN74AC10D
Contextual Info: TECHNICAL DATA IN74AC10 Triple 3-Input NAND Gate High-Speed Silicon-Gate CMOS The IN74AC10 is identical in pinout to the LS/ALS10, HC/HCT10. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS

Contextual Info: Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger 74LVC109 FEATURES DESCRIPTION • Wide supply voltage range of 1.2 to 3.6 V The 74LVC1G9 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT109.

"J-K Flip flop"

Abstract: CD54HC107F3A HC107 T flip flop IC CD54HC107 CD74HC107 CD74HC107E CD74HC107M CD74HCT107 HCT10
Contextual Info: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54HC107, CD74HC107, HCT107 Data sheet acquired from Harris Semiconductor SCHS139D Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised October 2003

74HC/HCT/HCU/HCMOS Logic Family Specifications

Abstract: 74HC/HCT/HCU/HCMOS Logic Package Information 74HC/HCT/HCU/HCMOS Logic Package Outlines IC06 74HC/HCT/HCU/HCMOS Logic Package Information Package Information philips IC06 74HC Logic Family Specifications logic family specification philips ic06 HCT10 IC06 74HC/HCT/HCU/HCMOS Logic Package Outline The IC06 74HC/HCT/HCU/HCMOS Logic Package
Contextual Info: INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT10

HC107

Abstract: CD54HC107 CD54HC107F3A CD74HC107 CD74HC107E CD74HC107M CD74HCT107 HCT10
Contextual Info: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54HC107, CD74HC107, HCT107 Data sheet acquired from Harris Semiconductor SCHS139C Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised May 2003

CD54HC10

Abstract: CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HC10E CD74HCT10 HC10 HCT10
Contextual Info: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54HC10, CD74HC10, HCT10, HCT10

Contextual Info: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54HC107, CD74HC107, HCT107 Data sheet acquired from Harris Semiconductor SCHS139D Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised October 2003

74hct10

Abstract: 74HC10
Contextual Info: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54/74HC10, CD54/HCT10 Data sheet acquired from Harris Semiconductor

KK74ACT10

Abstract: KK74ACT10D KK74ACT10N
Contextual Info: TECHNICAL DATA KK74ACT10 Triple 3-Input NAND Gate High-Speed Silicon-Gate CMOS The KK74ACT10 is identical in pinout to the LS/ALS10, HC/HCT10. The KK74ACT10 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. • TTL/NMOS Compatible Input Levels

CD74HC10E

Abstract: CD54HC10 CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HCT10 HC10 HCT10
Contextual Info: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54HC10, CD74HC10, HCT10, HCT10