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    74HCT10 Search Results

    74HCT10 Result Highlights (6)

    Part ECAD Model Manufacturer Description Download Buy
    CD74HCT10MT Texas Instruments High Speed CMOS Logic Triple 3-Input NAND Gates 14-SOIC -55 to 125 Visit Texas Instruments Buy
    CD74HCT10M96G4 Texas Instruments High Speed CMOS Logic Triple 3-Input NAND Gates 14-SOIC -55 to 125 Visit Texas Instruments Buy
    CD74HCT109M Texas Instruments High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125 Visit Texas Instruments Buy
    CD74HCT109M96 Texas Instruments High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125 Visit Texas Instruments
    CD74HCT10M96 Texas Instruments High Speed CMOS Logic Triple 3-Input NAND Gates 14-SOIC -55 to 125 Visit Texas Instruments Buy
    CD74HCT109E Texas Instruments High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125 Visit Texas Instruments Buy
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    74HCT10 Price and Stock

    Rochester Electronics LLC 74HCT107D-Q100J

    74HCT107 - DUAL JK FLIP-FLOP WIT
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    DigiKey 74HCT107D-Q100J Bulk 46,866 1,967
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    Rochester Electronics LLC 74HCT10D,652

    IC GATE NAND
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    DigiKey 74HCT10D,652 Bulk 46,208 2,357
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    Rochester Electronics LLC 74HCT10D/S400,118

    IC GATE NAND 3CH 3-INP 14SO
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    DigiKey 74HCT10D/S400,118 Bulk 15,000 3,493
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    Rochester Electronics LLC CD74HCT10MT

    IC GATE NAND 3CH 3-INP 14SOIC
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    DigiKey CD74HCT10MT Bulk 5,400 547
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    Rochester Electronics LLC 74HCT10DB,112

    IC GATE NAND
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    DigiKey 74HCT10DB,112 Bulk 4,056 1,293
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    74HCT10DB,112 Bulk 3,868 1,293
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    Find more 74HCT10 price and stock on Findchips.com

    74HCT10 Datasheets (75)

    Part ECAD Model Manufacturer Description Curated Type PDF
    74HCT10 Philips Semiconductors Triple 3-Input NAND Gate Original PDF
    74HCT107 Philips Semiconductors Dual JK flip-flop with reset negative-edge trigger Original PDF
    74HCT107D Philips Semiconductors Dual JK flip-flop with reset negative-edge trigger Original PDF
    74HCT107D Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    74HCT107D,652 NXP Semiconductors Dual JK flip-flop with reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Reset; Negative-Edge Trigger; TTL Enabled ; Fmax: 73 MHz; Logic switching levels: TTL ; Number of pins: 14 ; Output drive capability: +/- 4 mA ; Power dissipation considerations: Low Power ; Propagation delay: 16 ns; Voltage: 4.5-5.5V; Package: SOT108-1 (SO14); Container: Bulk Pack, CECC Original PDF
    74HCT107D,653 NXP Semiconductors Dual JK flip-flop with reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Reset; Negative-Edge Trigger; TTL Enabled ; Fmax: 73 MHz; Logic switching levels: TTL ; Number of pins: 14 ; Output drive capability: +/- 4 mA ; Power dissipation considerations: Low Power ; Propagation delay: 16 ns; Voltage: 4.5-5.5V; Package: SOT108-1 (SO14); Container: Reel Pack, SMD, 13", CECC Original PDF
    74HCT107DB Philips Semiconductors Dual JK Flip-Flop with Reset, Negative-Edge Trigger Original PDF
    74HCT107D-Q100 NXP Semiconductors Dual JK flip-flop with reset; negative-edge trigger Original PDF
    74HCT107D-Q100J NXP Semiconductors 74HCT107D-Q100 - 74HCT107D-Q100 - Dual JK flip-flop with reset; negative-edge trigger Original PDF
    74HCT107D-T Philips Semiconductors Dual JK flip-flop with reset negative-edge trigger Original PDF
    74HCT107D-T Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    74HCT107DW Philips Semiconductors Dual JK flip-flop with reset, negative-edge trigger Original PDF
    74HCT107N Philips Semiconductors Dual JK flip-flop with reset negative-edge trigger Original PDF
    74HCT107N Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    74HCT107N,652 NXP Semiconductors Dual JK flip-flop with reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Reset; Negative-Edge Trigger; TTL Enabled ; Fmax: 73 MHz; Logic switching levels: TTL ; Number of pins: 14 ; Output drive capability: +/- 4 mA ; Power dissipation considerations: Low Power ; Propagation delay: 16 ns; Voltage: 4.5-5.5V; Package: SOT27-1 (DIP14); Container: Bulk Pack, CECC Original PDF
    74HCT107PW Philips Semiconductors Dual JK Flip-Flop with Reset, Negative-Edge Trigger Original PDF
    74HCT107U Philips Semiconductors Dual JK flip-flop with reset negative-edge trigger Original PDF
    74HCT109 Philips Semiconductors Dual J invertedK flip-flop with set and reset positive-edge trigger Original PDF
    74HCT109D Philips Semiconductors Dual J Inverted(K)Flip-flop with Set and Reset, Positive-Edge Trigger Original PDF
    74HCT109D Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF

    74HCT10 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    74HC109

    Abstract: No abstract text available
    Text: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54/74HC109, CD54/74HCT109 Data sheet acquired from Harris Semiconductor SCHS140A Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised May 2000 Features


    Original     		PDF CD54/74HC109, CD54/74HCT109 SCHS140A HC109 HCT109 SCLA008 SZZU001B, SDYU001N, SCET004, SCAU001A, 74HC109

    CD74HCT107

    Abstract: CD54HC107F3A CD54HCT107F3A CD74HC107E HC107 HCT10
    Text: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54/74HC107, CD54/74HCT107 Data sheet acquired from Harris Semiconductor SCHS139B Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised December 2002


    Original     		PDF HC107 HCT10 CD54/74HC107, CD54/74HCT107 SCHS139B HC107 HCT107 CD74HCT107 CD54HC107F3A CD54HCT107F3A CD74HC107E HCT10

    HC-107

    Abstract: HC107
    Text: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54/74HC107, CD54/74HCT107 Data sheet acquired from Harris Semiconductor SCHS139A Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised May 2000 Features


    Original     		PDF HC107 HCT10 CD54/74HC107, CD54/74HCT107 SCHS139A HC107 HCT107 HC-107

    Untitled

    Abstract: No abstract text available
    Text: 74HC107; 74HCT107 Dual JK flip-flop with reset; negative-edge trigger Rev. 3 — 18 November 2013 Product data sheet 1. General description The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock CP and reset (R) inputs and complementary Q and Q


    Original     		PDF 74HC107; 74HCT107 74HCT107 HCT107

    Untitled

    Abstract: No abstract text available
    Text: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54/74HC109, CD54/74HCT109 Data sheet acquired from Harris Semiconductor SCHS140B Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised December 2002


    Original     		PDF CD54/74HC109, CD54/74HCT109 SCHS140B HC109 HCT109 CD74H CT109) 8415001EA CD54HC109F3A

    74hct10

    Abstract: 74HC10
    Text: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54/74HC10, CD54/74HCT10 Data sheet acquired from Harris Semiconductor


    Original     		PDF CD54/74HC10, CD54/74HCT10 SCHS128A HCT10 HCT10 SDYA012 SN54/74HCT SCLA011 SCLA008 SZZU001B, 74hct10 74HC10

    HCT109 harris

    Abstract: 74HCT109
    Text: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54/74HC109, CD54/74HCT109 Data sheet acquired from Harris Semiconductor SCHS140A Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised May 2000 Features


    Original     		PDF CD74H CT109) CD54/74HC109, CD54/74HCT109 SCHS140A HC109 HCT109 HCT109 harris 74HCT109

    74HC107PW

    Abstract: No abstract text available
    Text: 74HC107-Q100; 74HCT107-Q100 Dual JK flip-flop with reset; negative-edge trigger Rev. 1 — 18 November 2013 Product data sheet 1. General description The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock CP and reset (R) inputs and complementary Q


    Original     		PDF 74HC107-Q100; 74HCT107-Q100 74HCT107-Q100 HCT107 74HC107PW

    CD74HC109E

    Abstract: HC109 C109 CD54HC109F3A CD54HCT109F3A
    Text: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54/74HC109, CD54/74HCT109 Data sheet acquired from Harris Semiconductor SCHS140B Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised December 2002


    Original     		PDF CD74H CT109) CD54/74HC109, CD54/74HCT109 SCHS140B HC109 HCT109 CD74HC109E C109 CD54HC109F3A CD54HCT109F3A

    74HCT10

    Abstract: No abstract text available
    Text: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54/74HC10, CD54/74HCT10 Data sheet acquired from Harris Semiconductor


    Original     		PDF CD54/74HC10, CD54/74HCT10 SCHS128A HCT10 HCT10 59628984301CA CD54HCT10F3A 5962View 8984301CA 74HCT10

    74HC10

    Abstract: 74HCT10
    Text: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54/74HC10, CD54/74HCT10 Data sheet acquired from Harris Semiconductor


    Original     		PDF HCT10 CD54/74HC10, CD54/74HCT10 SCHS128A HCT10 74HC10 74HCT10

    HC-107

    Abstract: hc107
    Text: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54/74HC107, CD54/74HCT107 Data sheet acquired from Harris Semiconductor SCHS139B Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised December 2002


    Original     		PDF CD54/74HC107, CD54/74HCT107 SCHS139B HC107 HCT107 HC/HCT73 59628515401CA CD54HC107F3A 5962View 8515401CA HC-107

    125oCMIN

    Abstract: No abstract text available
    Text: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54/74HC107, CD54/74HCT107 Data sheet acquired from Harris Semiconductor SCHS139B Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised December 2002


    Original     		PDF CD54/74HC107, CD54/74HCT107 SCHS139B HC107 HCT107 HC/HCT73 125oCMIN

    74HC107

    Abstract: No abstract text available
    Text: Technical Data CD54/74HC107 CD54/74HCT107 File N u m b e r 1722 High-Speed CMOS Logic Dual J-K Flip-Flop with Reset N egative-E d g e T rigger Type Features: • zr GND * 7 v c c *14 92CS- 594 16 H y s te re s is o n c lo c k in p u ts fo r im p ro v e d n o is e im m u n ity a n d in c re a s e d


    OCR Scan     		PDF CD54/74HC107 CD54/74HCT107 CD54/74HCT107 54/74HC 54/74HCT 74HC107

    Untitled

    Abstract: No abstract text available
    Text: Technical Data_ _ CD54/74HC10 CD54/74HCT10 F ile N u m b e r 1551 High-Speed CMOS Logic Triple 3-Input NAND Gate Type Features: • B u ffe re d inputs ■ Typical propagation delay = 8 ns @ V c c = 5 V, CL = 75 pF, 7"a = 25° C


    OCR Scan     		PDF CD54/74HC10 CD54/74HCT10 54/74H 54/74HC

    74hct10

    Abstract: 74HC10 PF7A L68G
    Text: G Technical Data. E SOLI» STATE 01 j>r| 3fl7SDfll 0G114SS 4 - T ^ 3 - - Z I CD54/74HC10 CD54/74HCT10 File Number 1551 High-Speed CMOS Logic Triple 3-Input NAND Gate Type Feature«: • Buffered inputs a Typical propagation delay = 8ns


    OCR Scan     		PDF 0G114SS CD54/74HC10 CD54/74HCT10 RCA-CD54/74HC10 54HCT/74HCT 54LS/74LS CD54H1 54HCT 74HCT 74hct10 74HC10 PF7A L68G

    Untitled

    Abstract: No abstract text available
    Text: - Technical Data File N um b er 1667 CD54/74HC109 C D54/74HCT109 High-Speed CMOS Logic Duai J-K Flip-Flop with Set and Reset Type Features: 9 2 C S -36532 • Positive-Edge triggered • A s y n c h ro n o u s S et a n d Reset m 60 M Hz Typical M axim um C lo ck Frequency


    OCR Scan     		PDF CD54/74HC109 D54/74HCT109 54/74H 92CS-38533R2 92CS-38534R2 92CS-38535R2

    G0175

    Abstract: No abstract text available
    Text: Technical Data File N um ber CD54/74HC109 CD54/74HCT109 T-HL'-Q'l -01 1667 High-Speed CMOS Logic HARR IS S E M I C O N D S E CT OR to 27E D B 4 3 0 2 27 1 0 D 1 7 S M b 2 • HAS Dual J-K Flip-Flop with Set and Reset T yp e Features: 2J 2 K -H 2C P 12 VCC = 1 0


    OCR Scan     		PDF CD54/74HC109 CD54/74HCT109 92CS-38S3Z 54/74H 92CS-38533R2 92CS-38535R2 G0175

    GD74HCT10

    Abstract: GD74HC10
    Text: GD54/74HC10, GD54/74HCT10 TRIPLE 3-INPUT NAND GATES General Description These devices are identical in pinout to the 5 4 /74 L S 1 0. They contain three independent 3-input NAND gates. These devices are characteriz­ ed for operation over wide temperature ranges to


    OCR Scan     		PDF GD54/74HC10, GD54/74HCT10 GD74HCT10 GD54HCT10 GD74HCT10 GD74HC10

    Untitled

    Abstract: No abstract text available
    Text: GD54/74HC107, GD54/74HCT107 DUAL J-K FLIP-FLOPS WITH CLEAR General Description These devices are identical in pinout to the 5 4 /7 4 L S 1 0 7 . They consist of two J-K flip-flops with individual J, K, clock, and clear inputs. These flipflops are edge sensitive to the clock input and


    OCR Scan     		PDF GD54/74HC107, GD54/74HCT107

    Untitled

    Abstract: No abstract text available
    Text: Technical Data CD54/74HC107 CD54/74HCT107 File N um ber 1722 High-Speed CMOS Logic Dual J-K Flip-Flop with Reset N egative-E dge T rigg er Type Features: • _ x GNO • 7 Vcc ' 14 92CS - 39416 H ysteresis on c lo c k in p u ts fo r im proved noise im m u n ity a n d increased


    OCR Scan     		PDF CD54/74HC107 CD54/74HCT107 54/74HC 54/74HCT

    Untitled

    Abstract: No abstract text available
    Text: GD54/74HC109, GD54/74HCT109 DUAL J-K FLIP-FLOPS W ITH PRESET & CLEAR General Description are identical in pinout with individual J, K, Clock, Preset, to Pin Configuration the flip-flops and Clear U IC L R p T inputs. T h e s e flip-flops are e d g e sensitive to the


    OCR Scan     		PDF GD54/74HC109, GD54/74HCT109

    74HC107

    Abstract: No abstract text available
    Text: t-Hu-ch- r j Technical D ata _ — CD54/74HC107 CD54/74HCT107 r ile N u m b e r 1722 High-Speed CMOS Logic HARR IS S E M I C O N D S E CT OR 27E D 4 3 0 5 27 1 0 Q 1 7 S 4 1 E 3 •HAS Dual J-K Flip-Flop with Reset N egative-E d g e T rigg er


    OCR Scan     		PDF CD54/74HC107 CD54/74HCT107 74HC107

    74HCT10

    Abstract: No abstract text available
    Text: 1 ' 4 3 -Z/-CO Technical Data_ CD54/74HC10 CD54/74HCT10 HARRIS SEMICOND File Number 1551 SECTOR 27E D 430H271 0017475 5 *HAS High-Speed CMOS Logic Triple 3-Input NAND Gate Type Features: • B u tte re d inpu ts • Typical propagation delay = 8 ns @ Vcc = 5 V, CL = 15 pF, TA = 25° C


    OCR Scan     		PDF CD54/74HC10 CD54/74HCT10 430H271 54/74H 74HCT10