CY7C1021
Abstract: 7c1021
Text: 7c1021: March 31, 1995 Revised: June 25, 1996 ADVANCED INFORMATION 7C1021 64K x 16 Static RAM Features D Functional Description The 7C1021 is a highĆperformance CMOS static RAM organized as 65,536 words by 16 bits. Easy memory expansion is provided by an active LOW chip enable
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7c1021:
CY7C1021
CY7C1021
I/O15)
I/O15
7C1021-12
7C1021-15
7C1021-20
7c1021
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AS7C1024
Abstract: AL205 AS7C31024 IN317
Text: Hi gh Per for m an ce 128K 128 K x8 C M OS S R A M A S 7C1024 A S 7C31024 1288K ×8 CMOS S R A M 12 Features • Organization: 131,072 words × 8 bits • High speed - 10/12/15/20 ns address access time - 3/3/4/5 ns output enable access time • Low power consumption
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7C1024
7C31024
32-pin
7C512
AS7C1024
AL205
AS7C31024
IN317
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7C1024
Abstract: No abstract text available
Text: $6& 9.ð&02665$0 &RPPRQ,2 HDWXUHV • TTL-compatible, three-state I/O • 28-pin JEDEC standard packages - 300 mil PDIP and SOJ Socket compatible with 7C512 and 7C1024 - 8x13.4 TSOP • ESD protection ≥ 2000 volts • Latch-up current ≥ 200 mA
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28-pin
7C512
7C1024
AS7C256-12PC
AS7C256-15PC
AS7C256-20PC
AS7C256-10JC
AS7C256-12JC
AS7C256-12JI
AS7C256-15JC
7C1024
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CY7C1022
Abstract: No abstract text available
Text: Y7C10 PRELIMINARY 7C1022 32K x 16 Static RAM Features • 5.0V operation ± 10% • High speed — tAA = 12 ns • Low active power — 825 mW (max., 10 ns, “L” version) • Very Low standby power — 500 µW (max., “L” version) • Automatic power-down when deselected
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Y7C10
CY7C1022
400-mil
CY7C1022
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CY7C1020
Abstract: No abstract text available
Text: Y7C10 PRELIMINARY 7C1020 32K x 16 Static RAM Features BLE is LOW, then data from I/O pins (I/O 1 through I/O8), is written into the location specified on the address pins (A0 through A 14). If byte high enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A14).
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Y7C10
CY7C1020
I/O16)
44-pin
400-mil
44-Lead
400-Mil)
CY7C1020-15ZC
44-Lead
CY7C1020L-15ZC
CY7C1020
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ATPA
Abstract: 7130SA100P 24l01 7C263/4-35C 7164S15Y cy9122-25 7133SA35J 7142sa55 7130sa55p cy2149-45c
Text: Product Line Cross Reference CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS CY2147-35C CY7C147-35C CY7C147-45C CY7C147-35C CY91L22-35C CY7C122-35C CY2147-45C CY2147-35C CY7C148-35C CY7C148-25C+ CY91L22-45C CY93L422AC CY2147-45C CY7C147-45C CY7C148-45C CY7C148-35C
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CY2147-35C
CY7C147-35C
CY7C147-45C
CY91L22-35C
CY7C122-35C
CY2147-45C
CY7C148-35C
CY7C148-25C+
ATPA
7130SA100P
24l01
7C263/4-35C
7164S15Y
cy9122-25
7133SA35J
7142sa55
7130sa55p
cy2149-45c
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550mi
Abstract: No abstract text available
Text: 7c1021: March 31,1995 Revised: June 25,1996 7C1021 64K x 16 Static RAM ADVANCED INFORMATION Features Functional Description The 7C1021 is a high-performance CMOS static RAM organized as 65,536 words by 16 bits. Easy memory expansion is provided by an active LOW chip enable
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7c1021:
550-mil
CY7C1021
I/O13
I/O10
7C1021--12
7C1021--15
7C1021--20
550mi
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Untitled
Abstract: No abstract text available
Text: PRELIMINARY CYPRESS SEMICONDUCTOR Functional Description • High speed T he C Y 7C101A and CY 7C102A are highperform ance C M O S static R A M s orga nized as 262,144 x 4 bits with separate I/O. Easy m em ory expansion is provided by ac tive LO W chip enable C E and threestate drivers. B oth devices have an a u to
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CY7C101A
CY7C102A
7C101A)
7C101A
7C102A
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27C102JK
Abstract: No abstract text available
Text: M ITSUBISHI LSIs M5M2 7C102K, -12, -15, -2/ M 5M 7C102JK -1 2 ,-1 5 ,-2 1 0 4 8 5 7 6 -B IT 6 5 5 3 6 -W O R D BY 1 6 -B IT CMOS ERASABLE AND ELECTRICALLY REPROGRAMMABLE ROM DESCRIPTION T h e M itsub ishi M 5 M 2 7 C 1 0 2 K , J K is a high-speed 1 0 4 8 5 7 6 -
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7C102K,
M5M27C102JK
27C102JK
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AS7C512-20JC
Abstract: AS7C512-15PC VLN 2003 7C256 AS7C512
Text: AS7C512 5V 64K x8 CMOS SRAM 1Equal access and cycle tim es 1Easy m em ory expansion w ith CE1, CE2, OE inputs 1TTL-compatible, three-state I/O - 3 2-pin JEDEC standard packages - 300 m il PDIP and SOJ Socket com patible w ith 7C256 and 7C1024 1ESD p rotection > 2000 volts
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AS7C512
64Kx8
7C256
7C1024
256x256x8
TQ0344R
AS7C512-20JC
AS7C512-15PC
VLN 2003
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Untitled
Abstract: No abstract text available
Text: CY7C101A 7C102A PRELIMINARY CYPRESS SEMICONDUCTOR Features Functional Description • High speed T he C Y 7C101A and CY 7C102A are highp erform ance C M O S static R A M s orga nized as 262,144 x 4 bits w ith separate I/O . Easy m em ory expansion is provided by ac
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CY7C101A
CY7C102A
7C101A
7C102A
7C101A)
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M5M27C102jk
Abstract: 27C102K M5M27C102K-15 M5M27C102K-12 JK-15
Text: MITSUBISHI LSIs M5M2 7C102K, -12, -15,-2/ 7C102JK -12,-15,-2 1 0 4 8 5 7 6 -B IT 6 5 5 3 6 -W O R D BY 1 6 -B IT CMOS ERASABLE AND ELECTRICALLY REPROGRAMMABLE ROM DESCRIPTION The Mitsubishi M 5M 7C102K, J K is a high-speed 1048576- PIN C O N FIG U RATIO N (TOP V IEW )
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7C102K,
M5M27C102JK
27C102K,
1048576bit
M5M27C102K,
27C102K
M5M27C102K-15
M5M27C102K-12
JK-15
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CY7C101A
Abstract: CY7C102A 7C101A-12 l3lx
Text: PRELIMINARY 9 / C Y PR E SS CY7C101A 7C102A 256K x 4 Static RAM with Separate I/O Features Functional Description • High speed The CY7C101A and 7C102A are high perform ance CMOS static RAM s orga nized as 262,144 x 4 bits with separate I/O. Easy m emory expansion is p rovided by ac
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CY7C101A
CY7C102A
7C101A)
CY7C102A
CY7C101A
tdwel161
7C101A
8-00231-A
7C101A-12
l3lx
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Untitled
Abstract: No abstract text available
Text: Hij>h P e r f o r m, u h r AS7CI026 A » 64Kxl ' H C M O S SR AM AS7CÎI026 6 I k x If, CMOS NK'UI Preliminary information • O rg a n iz a tio n : 6 5 ,5 3 6 w o rd s x 16 bits • T T L - c o m p a tib le , three-state I / O • H ig h speed • 4 4 - p in JE D E C standard p ackage
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64Kxl(
AS7CI026
026-25TC
AS7C1026-20TC
\S7C1026
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Untitled
Abstract: No abstract text available
Text: High Performance 128Kx8 C M O S SRAM p i 7C1024 7C1024L 128Kx8 CM O S S RAM Common I/O FEATURES • Organization: 131,072 words x 8 bits • Equal access and cycle times • High speed • Easy memory expansion with CE1, CE2, OE inputs - 10/12/15/20/25/35 ns address access time
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128Kx8
AS7C1024
AS7C1024L
128Kx8
32-pin
7C256
7C512
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Untitled
Abstract: No abstract text available
Text: fax id: 1075 7C1020V _ Features 32Kx 16 Static RAM BLE is LOW, then data from I/O pins (l/0-| through l/0 8), is written into the location specified on the address pins (Aq through A 1 4 ). If byte high enable (BHE) is LOW, then data from I/O pins (l/Og through l/0-|6) is written into the location speci
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CY7C1020V
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Untitled
Abstract: No abstract text available
Text: 7C101A: 11-25-91 Revision: Thursday, February 18,1993 CY7C101A 7C102A k ' Vwt S3 « 3 PRELIMINARY 7J= CYPRESS SEMICONDUCTOR 256K x 4 Static RAM with Separate I/O Features Functional Description • Highspeed — tAA = 12 ns • Transparent write 7C101A
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7C101A:
CY7C101A
CY7C102A
7C101A)
CY7C101Aand
CY7C102Aare
in982.
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Untitled
Abstract: No abstract text available
Text: PRELIMINARY 7C1020 3 2 K x 16 Static RAM Features BLE is LOW, then data from I/O pins <l/0-| through l/0 8), is written into the location specified on the address pins (A0 through A14). If byte high enable (BHE) is LOW, then data from I/O pins (l/09 through l/0 16) is written into the location speci
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CY7C1020
44-pin
400-mil
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Untitled
Abstract: No abstract text available
Text: High Performance 32Kx8 CMOS SRAM p i AS7C256 AS7C256L 32Kx8 CMOS SRAM Common I/O FEATURES • Organization: 32,768 words x 8 bits Equal access and cycle times • High speed Easy memory expansion with CE and OE inputs - 10/12/15/20/25/35 ns address access time
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32Kx8
AS7C256
AS7C256L
32Kx8
28-pin
7C512
7C1024
versio-9177
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Untitled
Abstract: No abstract text available
Text: fax id: 1083 C 'i- PRELIMINARY 7C1021V30 64K Features X 16 Static RAM Writing to the device is accomplished by taking chip enable CE and write enable (WE) inputs LOW. If byte low enable (BEE) is LOW, then data from I/O pins (l/Oi through l/0 8), is written into the location specified on the address pins (A0
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CY7C1021V30
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Untitled
Abstract: No abstract text available
Text: 7C1021 P Yi. PX :V«*1 64K x 16 Static RAM BLE is LOW, then data from I/O pins (l/0-| through l/0 8), is written into the location specified on the address pins (A0 through A i5). If byte high enable (BHE) is LOW, then data from I/O pins (l/Og through I/0 1 6) is written into the location speci
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CY7C1021
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7C1024
Abstract: AS7C256
Text: AS7C256 5V 32K •8 CMOS SRAAA /Common I OV Features • O rganization: 3 2 ,7 6 8 w ords X 8 bits • H igh speed - 1 0 /1 2 /1 5 / 2 0 ns address access tim e - 3 / 3 / 4 / 5 ns o utput enable access tim e • Low pow er consum ption - Active: 660 m W m ax 10 ns cycle
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AS7C256
7C512
7C1024
1DD344
AS7C256
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Untitled
Abstract: No abstract text available
Text: H ig h P erfo rm a n ce 32K X8 CMOS SRAM AS7C.256 AS7C 256L A 32KX8 CMOS SRAM Common I/O • Organization: 32,768 words x 8 bits •H ig h sp eed - 1 0 /1 2 /1 5 /2 0 /2 5 /3 5 ns address access time - 3 / 3 / 4 / 5 / 6 /8 ns output enable access time • Low power consumption
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32KX8
7C512
7C1024
AS7C256
S7C256L-20SC
AS7C256L-2SSC
AS7C256L-35SC
S7C2S6-12TC
S7C256-15TC
S7C256-20TC
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Untitled
Abstract: No abstract text available
Text: High Performance 128KX8 CMOS SRAM 7C1024 AS7C31024 128KX8 CMOS SRAM Features • Organization: 131,072 words x 8 bits • High speed - 1 0 / 1 2 / 1 5 / 2 0 / 2 5 ns address access time - 3 / 3 / 4 / 5 / 6 ns output enable access time • Low power consumption
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128KX8
AS7C1024
AS7C31024
128KX8
7C512
1003MIH
DDDDM13
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