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    7C1021 Price and Stock

    Infineon Technologies AG CY7C1021DV33-10BVXIT

    IC SRAM 1MBIT PARALLEL 48VFBGA
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    DigiKey CY7C1021DV33-10BVXIT Digi-Reel 1,961 1
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    CY7C1021DV33-10BVXIT Cut Tape 1,961 1
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    Avnet Americas CY7C1021DV33-10BVXIT Reel 8 Weeks 2,000
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    Mouser Electronics CY7C1021DV33-10BVXIT 957
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    Newark CY7C1021DV33-10BVXIT Cut Tape 1
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    Chip One Stop CY7C1021DV33-10BVXIT Cut Tape 2,000
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    Infineon Technologies AG CY7C1021DV33-10ZSXIT

    IC SRAM 1MBIT PARALLEL 44TSOP II
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    DigiKey CY7C1021DV33-10ZSXIT Digi-Reel 1,753 1
    • 1 $3.05
    • 10 $2.709
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    CY7C1021DV33-10ZSXIT Cut Tape 1,753 1
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    CY7C1021DV33-10ZSXIT Reel 1,000 1,000
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    Mouser Electronics CY7C1021DV33-10ZSXIT 1,509
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    Chip One Stop CY7C1021DV33-10ZSXIT Cut Tape 1,983
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    EBV Elektronik CY7C1021DV33-10ZSXIT 9 Weeks 1,000
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    Infineon Technologies AG CY7C1021DV33-10VXIT

    IC SRAM 1MBIT PARALLEL 44SOJ
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    DigiKey CY7C1021DV33-10VXIT Cut Tape 895 1
    • 1 $3.05
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    CY7C1021DV33-10VXIT Digi-Reel 895 1
    • 1 $3.05
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    • 100 $2.4038
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    CY7C1021DV33-10VXIT Reel 500 500
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    • 10000 $1.96101
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    Avnet Americas CY7C1021DV33-10VXIT Reel 8 Weeks 500
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    Mouser Electronics CY7C1021DV33-10VXIT 869
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    Chip One Stop CY7C1021DV33-10VXIT Cut Tape 500
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    EBV Elektronik CY7C1021DV33-10VXIT 9 Weeks 500
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    Infineon Technologies AG CY7C1021DV33-10VXI

    IC SRAM 1MBIT PARALLEL 44SOJ
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    DigiKey CY7C1021DV33-10VXI Tube 538 1
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    Mouser Electronics CY7C1021DV33-10VXI 70
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    Newark CY7C1021DV33-10VXI Bulk 444 1
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    Chip One Stop CY7C1021DV33-10VXI Tube 4
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    EBV Elektronik CY7C1021DV33-10VXI 9 Weeks 510
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    Cypress Semiconductor CY7C1021DV33-10BVXI

    NO WARRANTY
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey CY7C1021DV33-10BVXI Tray 485 1
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    Newark CY7C1021DV33-10BVXI Bulk 1
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    7C1021 Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    CY7C1021

    Abstract: 7c1021
    Text: 7c1021: March 31, 1995 Revised: June 25, 1996 ADVANCED INFORMATION 7C1021 64K x 16 Static RAM Features D Functional Description The 7C1021 is a highĆperformance CMOS static RAM organized as 65,536 words by 16 bits. Easy memory expansion is provided by an active LOW chip enable


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    7c1021: CY7C1021 CY7C1021 I/O15) I/O15 7C1021-12 7C1021-15 7C1021-20 7c1021 PDF

    ATPA

    Abstract: 7130SA100P 24l01 7C263/4-35C 7164S15Y cy9122-25 7133SA35J 7142sa55 7130sa55p cy2149-45c
    Text: Product Line Cross Reference CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS CY2147-35C CY7C147-35C CY7C147-45C CY7C147-35C CY91L22-35C CY7C122-35C CY2147-45C CY2147-35C CY7C148-35C CY7C148-25C+ CY91L22-45C CY93L422AC CY2147-45C CY7C147-45C CY7C148-45C CY7C148-35C


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    CY2147-35C CY7C147-35C CY7C147-45C CY91L22-35C CY7C122-35C CY2147-45C CY7C148-35C CY7C148-25C+ ATPA 7130SA100P 24l01 7C263/4-35C 7164S15Y cy9122-25 7133SA35J 7142sa55 7130sa55p cy2149-45c PDF

    CY7C1021BN-15VI

    Abstract: CY7C1021BN
    Text: 7C1021BN 7C10211BN 1-Mbit 64K x 16 Static RAM Features Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0


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    CY7C1021BN CY7C10211BN I/O16) CY7C1021BN/CY7C10211BN CY7C1021BN-15VI CY7C1021BN PDF

    CY7C1021BN

    Abstract: No abstract text available
    Text: 7C1021BN 7C10211BN 1-Mbit 64K x 16 Static RAM Features Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0


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    CY7C1021BN CY7C10211BN I/O16) CY7C1021BN/CY7C10211BN CY7C1021BN PDF

    Untitled

    Abstract: No abstract text available
    Text: 7C1021D PRELIMINARY 1-Mbit 64K x 16 Static RAM Features automatic power-down feature that significantly reduces power consumption when deselected. • Pin- and function-compatible with 7C1021B • High speed — tAA = 10 ns • CMOS for optimum speed/power


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    CY7C1021D CY7C1021B 44-pin 400-mil CY7C1021D PDF

    CY7C1021V30

    Abstract: CY7C1021V30-15BSI
    Text: fax id: 1083 1CY 7C10 21 V ADVANCED INFORMATION 7C1021V30 64K x 16 Static RAM Features • 3.0V operation 2.7V–3.3V • High speed — tAA = 15 ns • CMOS for optimum speed/power • Low active power (L version) — 462 mW (max.) • Low CMOS Standby Power (L version)


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    CY7C1021V30 CY7C1021V30 CY7C1021V30-15BSI PDF

    CY7C1021BV

    Abstract: CY7C1021BV33
    Text: 7C1021BV33 7C1021BV33 64K x 16 Static RAM Features Writing to the device is accomplished by taking Chip Enable CE and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0


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    1CY7C1021BV33 CY7C1021BV33 I/O16) CY7C1021BV CY7C1021BV33 PDF

    CY7C1021B-15ZSXE

    Abstract: CY7C1021B-12ZXC CY7C1021B
    Text: 7C1021B 1-Mbit 64K x 16 Static RAM Features automatic power-down feature that significantly reduces power consumption when deselected. • Temperature Ranges Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable


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    CY7C1021B I/O16) CY7C10211B CY7C1021B-15ZSXE CY7C1021B-12ZXC CY7C1021B PDF

    CY7C1021V33-15VI

    Abstract: 1021V-10 CY7C1021V33L-15ZI CY7C1021V33 CY7C1021V CY7C1021V33-12ZC CY7C1021V33L15ZI CY7C1021V33L15BAC CY7C1021V33-12BAI
    Text: fax id: 1077 7C1021V 64K x 16 Static RAM Features Writing to the device is accomplished by taking chip enable CE and write enable (WE) inputs LOW. If byte low enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0


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    CY7C1021V I/O16) CY7C1021V33-15VI 1021V-10 CY7C1021V33L-15ZI CY7C1021V33 CY7C1021V CY7C1021V33-12ZC CY7C1021V33L15ZI CY7C1021V33L15BAC CY7C1021V33-12BAI PDF

    CY7C1021V33-12ZC

    Abstract: cy7c1021v33-15zi CY7C1021V33-10VC CY7C1021V CY7C1021V33-10ZC
    Text: fax id: 1077 1CY 7C10 21 V PRELIMINARY 7C1021V 64K x 16 Static RAM Features Writing to the device is accomplished by taking chip enable CE and write enable (WE) inputs LOW. If byte low enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is


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    CY7C1021V I/O16) CY7C1021V33-12ZC cy7c1021v33-15zi CY7C1021V33-10VC CY7C1021V CY7C1021V33-10ZC PDF

    EPM5128LC

    Abstract: IDT CYPRESS CROSS REFERENCE clocks epm5064lc-1 EPM5128LC-1 EPM5064LC EPM5128LC-2 EPM5128GI EPM5128JC-1 8464c 5962-8871309
    Text: Product Line Cross Reference CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS CY2148-35C CY21L48-35C CY7C168A-35C CY7C168A-25C 5962-8871309XX 5962-89839112X CY2148-35C CY7C148-35C CY7C168A-45M CY7C168A-35M+ 5962-8871310RX 5962-8983913RX CY2148-35M CY7C148-35M CY7C169A-35C


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    CY2148-35C CY21L48-35C CY7C168A-35C CY7C168A-25C 5962-8871309XX 5962-89839112X CY7C148-35C CY7C168A-45M CY7C168A-35M+ EPM5128LC IDT CYPRESS CROSS REFERENCE clocks epm5064lc-1 EPM5128LC-1 EPM5064LC EPM5128LC-2 EPM5128GI EPM5128JC-1 8464c 5962-8871309 PDF

    15BAI

    Abstract: No abstract text available
    Text: 33 7C1021BV33 PRELIMINARY 64K x 16 Static RAM Features Writing to the device is accomplished by taking Chip Enable CE and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O 1 through I/O8), is written into the location specified on the address pins (A0


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    CY7C1021BV33 44-pin 400-mil 48-Ball 15BAI PDF

    7C1021B-15

    Abstract: 10211B CY7C1021B-12VC CY7C10211B CY7C1021B
    Text: 0211B 7C1021B/ 7C10211B 64K x 16 Static RAM Features • High speed — tAA = 10, 12, 15 ns • CMOS for optimum speed/power • Low active power — 825 mW max. • Automatic power-down when deselected • Independent control of upper and lower bits


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    0211B CY7C1021B/ CY7C10211B 44-pin 400-mil CY7C1021B/10211B CY7C1021B CY7C10211B 7C1021B-15 10211B CY7C1021B-12VC PDF

    CY7C10211B

    Abstract: CY7C1021B
    Text: 7C1021B 7C10211B 1-Mbit 64K x 16 Static RAM Features Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0


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    CY7C1021B CY7C10211B I/O16) CY7C1021B/CY7C10211B CY7C10211B CY7C1021B PDF

    verilog for SRAM 512k word 16bit

    Abstract: CY62512V CYM74P436 192-Macrocell 62128 sram 7C1350 Triton P54C palce16v8 programming guide 7C168A intel 16k 8bit RAM chip
    Text: Product Selector Guide Static RAMs Organization/Density Density X1 X4 4K X8 X9 X16 X18 X32 X36 7C148 7C149 7C150 16K 7C167A 7C168A 7C128A 6116 64K to 72K 7C187 7C164 7C166 7C185 6264 7C182 256K to 288K 7C197 7C194 7C195 7C199 7C1399/V 62256/V 62256V25 62256V18


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    7C148 7C149 7C150 7C167A 7C168A 7C128A 7C187 7C164 7C166 7C185 verilog for SRAM 512k word 16bit CY62512V CYM74P436 192-Macrocell 62128 sram 7C1350 Triton P54C palce16v8 programming guide 7C168A intel 16k 8bit RAM chip PDF

    550mi

    Abstract: No abstract text available
    Text: 7c1021: March 31,1995 Revised: June 25,1996 7C1021 64K x 16 Static RAM ADVANCED INFORMATION Features Functional Description The 7C1021 is a high-performance CMOS static RAM organized as 65,536 words by 16 bits. Easy memory expansion is provided by an active LOW chip enable


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    7c1021: 550-mil CY7C1021 I/O13 I/O10 7C1021--12 7C1021--15 7C1021--20 550mi PDF

    7C1021

    Abstract: C2223 ge639 A12C CY7C1021
    Text: CYPRESS Features • 12 ns • C M O S for optim um speed/pow er • L ow active power — 1020 mW • A vailable in 450 x 550-m il LCC • A utom atic power-down w hen deselected • E asy m em ory exp an sion w ith C Ej, CE 2, and O E options 7C1021 64K x 16 Static RAM


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    CY7C1021 550-mil CY7C1021 l/016 7C1021 7C102Xâ 7C1021 C2223 ge639 A12C PDF

    Untitled

    Abstract: No abstract text available
    Text: fax id: 1083 C 'i- PRELIMINARY 7C1021V30 64K Features X 16 Static RAM Writing to the device is accomplished by taking chip enable CE and write enable (WE) inputs LOW. If byte low enable (BEE) is LOW, then data from I/O pins (l/Oi through l/0 8), is written into the location specified on the address pins (A0


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    CY7C1021V30 PDF

    Untitled

    Abstract: No abstract text available
    Text: 7C1021 P Yi. PX :V«*1 64K x 16 Static RAM BLE is LOW, then data from I/O pins (l/0-| through l/0 8), is written into the location specified on the address pins (A0 through A i5). If byte high enable (BHE) is LOW, then data from I/O pins (l/Og through I/0 1 6) is written into the location speci­


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    CY7C1021 PDF

    7C1021-10

    Abstract: No abstract text available
    Text: 7C1021 64K x 16 Static RAM BLE is LOW, then data from I/O pins (l/0-| through l/Os), is written into the location specified on the address pins (A0 through A 15). If byte high enable (BHE) is LOW, then data from I/O pins (l/Og through l/0 16) is written into the location speci­


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    CY7C1021 44-pin 400-mil 7C1021-10 PDF

    Untitled

    Abstract: No abstract text available
    Text: fax id: 1083 C Y 7 C 1 0 2 1 V 3 0 64K X 16 Static RAM Writing to the device is accomplished by taking chip enable UE and write enable (WE) inputs LOW. If byte low enable (BLE) is LOW, then data from I/O pins ( l/0 1 through l/0 8), is written into the location specified on the address pins (A0


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    PDF

    Untitled

    Abstract: No abstract text available
    Text: 1I S 8 K J F P 7C1021 YJl xP 1 RiXJjEkw/i^ F ^ _ — 64K x 16 Static RAM BLE is LOW, then data from I/O pins (l/0 1 through l/0 8), is written into the location specified on the address pins (A0 through A i5). If byte high enable (BHE) is LOW, then data from


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    CY7C1021 PDF

    A12C

    Abstract: A14C A15C CY7C1021V
    Text: fax id: 1077 C Y7C 1021V 64K x 16 Static RAM Features Writing to the device is accomplished by taking chip enable CE and write enable (WE) inputs LOW. If byte low enable (BLE) is LOW, then data from I/O pins (l/O-i through l/Og), is written into the location specified on the address pins (Aq


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    44-pin 400-mil CY7C1021V CY7C1021V A12C A14C A15C PDF

    A13L

    Abstract: CY7C1021V
    Text: 7C1021V V CYPRESS 64K x 16 Static RAM Features W riting to th e device is a c c o m plished by takin g chip ena b le CE and w rite enable (W E) inputs LOW. If byte low enable (BLE) is LOW, then data from I/O pins (l/O-i throu gh l/O g ), is w ritten into the location sp e cified on the address pins (A0


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    CY7C1021V 44-pin 400-mil 48-Ball CY7C1021V A13L PDF