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    74LS40P Search Results

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    74LS40P Price and Stock

    Fairchild Semiconductor Corporation 74LS40PC

    74LS40 - NAND Gate, TTL, PDIP14 '
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Rochester Electronics 74LS40PC 249 1
    • 1 $0.182
    • 10 $0.182
    • 100 $0.1711
    • 1000 $0.1547
    • 10000 $0.1547
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    74LS40P Datasheets (1)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    74LS40PC Fairchild Semiconductor Dual 4-Input NAND Buffer Scan PDF

    74LS40P Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    20-PIN

    Abstract: M74LS40P
    Text: MITSUBISHI LSTTLs M 74LS40P DUAL 4 -IN P U T P O S ITIV E NAND BUFFER DESCRIPTION The M 7 4L S 40 P is a semiconductor integrated PIN CONFIGURATION TOP VIEW circuit containing 2 built-in quadruple-input positive N A N D and negative N O R buffer gates. - H


    OCR Scan     		PDF M74LS40P 0013Sbl 20-PIN M74LS40P

    74LS40

    Abstract: 74LS40D IC 7440
    Text: 40 CO NNECTIO N DIAGRAMS PINOUT A 54/7440 0 '° / l^ H / 7 4 H 4 0 o n o ^ 'v ^ 4 S / 7 4 S4 0 o / f c L/'l ^54LS/74LS40 C'Oi DUAL 4-INPUT NAND BUFFER ORDERING CODE: See Section 9 PIN PKGS OUT CO M M ERCIAL GRADE M ILITARY GRADE Vcc = +5.0 V ±5%, T a = 0 °C to +70° C


    OCR Scan     		PDF 54LS/74LS40 7440PC, 74H40PC 74S40PC, 74LS40PC 7440DC, 74H40DC 74S40DC, 74LS40DC 74S40FC, 74LS40 74LS40D IC 7440

    74H40DC

    Abstract: 74LS40 7440PC
    Text: NATIONAL SEHICOND -CLOGIO OSE D | 1,501152 0 0 b 3 b ? 0 h | 4 0 CO NNECTIO N DIAGRAMS PINOUT A 54/7440 54H/74H40 54S/74S40 54LS/74LS40 DUAL 4-1NPUT NAND BUFFER ORDERING CODE: See S ection 9 PIN PKGS OUT


    OCR Scan     		PDF 54H/74H40 54S/74S40 54LS/74LS40 7440PC, 74H40PC 74S40PC. 74LS40PC 7440DC, 74H40DC 74S40DC, 74LS40 7440PC

    74ls40dc

    Abstract: 74LS40 7440DC 7440PC 74H40DC 74H40PC 74LS40PC 74S40DC 74S40PC 74S40
    Text: 40 C O N N E C T IO N D IA G R A M S P IN O U T A 54/7440 ä>'°/ vé$JH/74H40 ¡9// o ' / i , ~v^>4S/74S40 O f f c c/'l ^54LS /74LS 40 ^ y DUAL 4-IN PU T NAND BUFFER O R D E R IN G C O D E : See S e c tio n 9 PIN PK G S OUT C O M M E R C IA L G RADE M IL IT A R Y G RADE


    OCR Scan     		PDF H/74H40 4S/74S40 /54LS/74LS40 7440PC, 74H40PC 74S40PC, 74LS40PC 7440DC, 74H40DC 74S40DC, 74ls40dc 74LS40 7440DC 7440PC 74LS40PC 74S40DC 74S40PC 74S40

    100414DC

    Abstract: 5401DM Fairchild dtl catalog fsa2719m 4727BPC FCM7010 FCM7004 937DMQB fairchild rtl FSA2501
    Text: FAIRMONT ELECTRONICS PTY. LTD. TE L.48-6421 4 8 -6 4 8 1 /2 /4 C AB LES ' FAIRTRONICS' C R A IG H A L L T E L E X 8-3227 S A . P O .BOX 41102, C R A IG H A LL 2024. I ouani v-ox 39! 262Bramley 2018 FAIRCHILD 464 Ellis Street, M ountain View, C alifornia 94042


    OCR Scan     		PDF 262Bramley orporation/464 962-5011/TWX 19-PIN 100414DC 5401DM Fairchild dtl catalog fsa2719m 4727BPC FCM7010 FCM7004 937DMQB fairchild rtl FSA2501

    74LS40P

    Abstract: No abstract text available
    Text: MITSUBISHI LSTTLs 74LS40P DUAL 4 -IN P U T P O S ITIV E NAND BUFFER DESCRIPTION The M 7 4L S 40 P is a semiconductor integrated PIN CONFIGURATION TOP VIEW circuit containing 2 built-in quadruple-input positive N A N D and negative N O R buffer gates. - H


    OCR Scan     		PDF M74LS40P 500ns, 0013Sbl 74LS40P