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    74LS12 Search Results

    74LS12 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    74LS12N Rochester Electronics LLC NAND Gate, LS Series, 3-Func, 3-Input, TTL, PDIP14 Visit Rochester Electronics LLC Buy
    74LS123P-E Renesas Electronics Corporation HD74LS Series Visit Renesas Electronics Corporation
    74LS125AFPEL-E Renesas Electronics Corporation HD74LS Series Visit Renesas Electronics Corporation
    74LS12P-E Renesas Electronics Corporation HD74LS Series, , / Visit Renesas Electronics Corporation
    74LS125AP-E Renesas Electronics Corporation HD74LS Series Visit Renesas Electronics Corporation
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    74LS12 Price and Stock

    Rochester Electronics LLC SN74LS122N

    SN74LS122 RETRIGGERABLE MONOSTAB
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    DigiKey SN74LS122N Bulk 43,266 440
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    Rochester Electronics LLC 74LS12N

    IC GATE NAND 3CH 3-INP 14DIP
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    DigiKey 74LS12N Bulk 12,962 11
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    Rochester Electronics 74LS12N 12,962 1
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    Rochester Electronics LLC SN74LS123DB

    IC MULTIVIBRATOR
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    DigiKey SN74LS123DB Bulk 9,040 513
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    Rochester Electronics LLC SN74LS123DBR

    SN74LS123 DUAL RETRIGGERABLE MON
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    DigiKey SN74LS123DBR Bulk 5,488 971
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    Rochester Electronics LLC SN74LS122NS

    IC RE-TRIG MONO MULTIVIB 14SO
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    DigiKey SN74LS122NS Bulk 4,750 987
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    Find more 74LS12 price and stock on Findchips.com

    74LS12 Datasheets (45)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    74LS12 Fairchild Semiconductor Dual Retriggerable One-Shot with Clear and Complementary Outputs Original PDF
    74LS12 Hitachi Semiconductor Dual Retriggerable Monostable Multivibrators(with Clear) Original PDF
    74LS12 Motorola RETRIGGERABLE MONOSTABLE MULTIVIBRATORS Original PDF
    74LS12 On Semiconductor LOW POWER SCHOTTKY Original PDF
    74LS12 Texas Instruments TRIPLE 3-INPUT POSITIVE-NAND GATES WITH COLLECTOR OUTPUTS Original PDF
    74LS12 Raytheon Positive-NAND Gates, Hex Inverters With Open-Collector Outputs Scan PDF
    74LS12 Signetics Integrated Circuits Catalogue 1978/79 Scan PDF
    74LS122 Hitachi Semiconductor Retriggerable Monostable Multivibrators(with Clear) Original PDF
    74LS122 On Semiconductor LOW POWER SCHOTTKY Original PDF
    74LS122 Texas Instruments RETRIGGERABLE MONOSTABLE MULTIVIBRATORS Original PDF
    74LS122 Raytheon Single and Dual Retriggerable Monostable Multivibrators with Clear Scan PDF
    74LS123 Fairchild Semiconductor Dual Retriggerable One-Shot with Clear and Complementary Outputs Original PDF
    74LS123 Texas Instruments RETRIGGERABLE MONOSTABLE MULTIVIBRATORS Original PDF
    74LS123 Raytheon Single and Dual Retriggerable Monostable Multivibrators with Clear Scan PDF
    74LS123 Signetics Integrated Circuits Catalogue 1978/79 Scan PDF
    74LS123M Unknown TTL Data Book 1980 Scan PDF
    74LS124 Texas Instruments VOLTAGE-CONTROLLED OSCILLATORS Original PDF
    74LS125 Fairchild Semiconductor Quad 3-STATE Buffer Original PDF
    74LS125 Hitachi Semiconductor Quadriple Bus Buffer Gates(with three-state outputs) Original PDF
    74LS125 Motorola QUAD 3-STATE BUFFERS Original PDF

    74LS12 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    ls125a

    Abstract: ls126A 74LS126A 751A-02 SN54LSXXXJ SN74LSXXXD SN74LSXXXN
    Text: SN54/74LS125A SN54/74LS126A QUAD 3-STATE BUFFERS VCC E D O E D O 14 13 12 11 10 9 8 QUAD 3-STATE BUFFERS LOW POWER SCHOTTKY 1 2 3 E D O 4 5 6 7 E D O GND LS125A J SUFFIX CERAMIC CASE 632-08 VCC E D O E D O 14 13 12 11 10 9 8 14 1 N SUFFIX PLASTIC CASE 646-06


    Original     		PDF SN54/74LS125A SN54/74LS126A LS125A LS126A 51A-02 SN54LSXXXJ SN74LSXXXN SN74LSXXXD ls125a ls126A 74LS126A 751A-02 SN54LSXXXJ SN74LSXXXD SN74LSXXXN

    74126PC

    Abstract: 74126DC 74LS126PC 74LS126DC 74LS126 54126DM 54126FM 54LS126DM 54LS126FM 74126FC
    Text: 126 CO NN ECTIO N DIAGRAM PINOUT A Ol 54/74126 0 i 0 54LS/74LS126 QUAD BUS BUFFER GATE With 3-State Outputs ORDERING CODE: See Section 9 PIN PKGS OUT COMMERCIAL GRADE MILITARY GRADE Vcc = +5.0 V ±5%, T a = 0°C to +70° C Vcc = +5.0 V ±10%, T a = -55° C to +125°C


    OCR Scan     		PDF 54LS/74LS126 74126PC 74LS126PC 74126DC, 74LS126DC 74126FC, 74LS126FC 54126DM, 54LS126DM 54126FM, 74126DC 74LS126PC 74LS126DC 74LS126 54126DM 54126FM 54LS126DM 54LS126FM 74126FC

    SO-140

    Abstract: DN74LS12
    Text: DN74LS1 2 LS TTL DN74LS Series 74LS12 T rip le 3 - input P o sitiv e NAND G ates with Open C ollector Outputs • Description P-1 DN 74LS12 contains three 3-input positive isolation NAND gate circuits w ith open collector outputs. ■ Features • •


    OCR Scan     		PDF DN74LS DN74LS1 DN74LS12 DN74LS12 14-pin SO-14D) SO-140

    DN74LS125A

    Abstract: MA161
    Text: I LS TTL DN74LS Series 74LS125A 74LS125A Quad Bus Buffer Gates with 3 -sta te Outputs • Description P-1 DN 74LS125A contains four 3-state o u tp u t b uffer gate circuits, each w ith independent o u tp u t-co n tro l input-C term inals. ■ Features


    OCR Scan     		PDF DN74LS DN74LS125 DN74LS125A DN74LS125A 14-pin SO-14D) MA161

    M74LS126AP

    Abstract: 20-PIN 12kf
    Text: MITSUBISHI LSTTLs M 74LS126AP Q U AD R U PLE BU S BU FFER G A TE WITH 3-STA TE O UTPUT DESCRIPTION PIN CONFIGURATION TOP VIEW The M 74LS126AP is a semiconductor integrated circuit containing 4 buffers w ith 3-state outputs and is provided w ith an o u tp u t control in p u t OC which is independent fo r


    OCR Scan     		PDF M74LS126AP M74LS126AP 16-PIN 20-PIN 12kf

    74s124

    Abstract: 74LS124 74124 LS124 74*124 VCO104 RC1V
    Text: - 98- 74124 Dual V C O vcc vcc «W C „, C «„ 10~4 74LS124 fo = -^ — 74S124 fo = C txt 5 X 1 0 "4 c^r 2 — lO p F L S 1 2 4 5 -1 5 p F ( S124) . 7 « , _ 1 ' I ' IG IV OGND ENABLE OUTPUT J f ia fnax * * min Kh FC=4V fmax •in FC=1V fiBin ain


    OCR Scan     		PDF 74LS124 74S124 LS124) 74s124 74124 LS124 74*124 VCO104 RC1V

    Untitled

    Abstract: No abstract text available
    Text: LS TTL DN74LS Series 74LS125A 74LS125A > IS a s A Quad Bus Buffer Gates with 3 -sta te Outputs • Description P-1 D N 74LS125A c o n ta in s c irc u its , each te rm in a ls. w ith f o u r 3 -sta te in d e p e n d e n t o u tp u t b u ff e r gate o u tp u t- c o n tr o l


    OCR Scan     		PDF DN74LS DN74LS125A 74LS125A

    CASE-646

    Abstract: truth table NAND gate 74 751A-02
    Text: g M O TO R O LA SN54/74LS12 TRIPLE 3-INPUT NAND GATE TR IP LE 3-IN P U T NAND GATE V cc ra fïïi ra nn N m m LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 632-08 Ll I Ll J Ll I 1_l I Ll I Ll I Ll I GND •OPEN COLLECTOR OUTPUTS •HÜB N SUFFIX PLASTIC CASE 646-06


    OCR Scan     		PDF SN54/74LS12 51A-02 SN54LSXXJ SN74LSXXN SN74LSXXD -18mA CASE-646 truth table NAND gate 74 751A-02

    Untitled

    Abstract: No abstract text available
    Text: 54/7412 54LS/74LS12 ORDERING CODE PACKAGES PIN C O N F. PIN CONFIGURATION See Section 9 for further Package and Ordering Information. C O M M ERCIAL R A N G ES =5V ±5%; T a =0“C to *70"C VC C Plastic D IP Fig. A N7412N • 74LS12N Ceramic D IP Fig. A


    OCR Scan     		PDF 54LS/74LS12 N7412N N7412F N74LS12F N74LS12N S5412F S5412W S54LS12W 54H/74H 54LS/74LS

    LS126A

    Abstract: No abstract text available
    Text: g MOTOROLA SN54LS/74LS125A SN54LS/74LS126A TRUTH TABLES L S 125A INPUTS LS126A INPUTS E H L H H X L O UTPUT T D L L L H H H X (Z) L OUTPUT L H (2) Q UAD 3-STATE BUFFERS LOW POWER SCHOTTKY L ” LOW Voltage Level H - H IG H V oltage Level X “ D o n 't Care


    OCR Scan     		PDF SN54LS/74LS125A SN54LS/74LS126A LS126A LS126A --------13V

    Untitled

    Abstract: No abstract text available
    Text: PANASONIC INDL/ELEK -CIO 72 • - - . . ■ , T È I h13SñS2 GDD7025 □ 1 ~ JH _ _ 693285 2 PANASONIC INOL t E L ECTRONIC 72C LS TTL DN74LSS/U-X 07Q25 B D N 74LSÌ 26A/D N 74LS126AS 74LS126A/74LS126AS Quad Bus Buffer Gates with 3-state Outputs


    OCR Scan     		PDF GDD7025 07Q25 DN74LS126A/DN74LS126AS DN74LSS/U-X 74LS126AS 14-DIP S0-14D hT32flS2 DDQ7027 DN74LS'

    74LS125APC

    Abstract: 74LS125AP 74LS125AFC
    Text: ! NATIONAL SENICOND {LOGIC} D5E D I t.SG1125 00^3003 □ I T -m s- ¿5 .fé CO NN ECTIO N DIAGRAM PINOUT A 54/74125 54LS/74LS125A QUAD BUS BUFFER GATE With 3-State Outputs ORDERING CODE: See Section 9 PIN PKGS COM MERCIAL GRADE MILITARY GRADE Vcc = +5.0 V ±5%,


    OCR Scan     		PDF SG1125 54LS/74LS125A 74125PC, 74LS125APC 74125DC, 74LS125ADC 74125FC, 74LS125AFC 54125DM, 54LS125ADM 74LS125AP

    Untitled

    Abstract: No abstract text available
    Text: GD54/74LS123 DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS WITH CLEAR Feature Pin Configuration • • D-C Triggered from active-hign or active-low gated logic inputs Retriggerable for very long output pulses, up to 100% duty cycle • Overriding clear terminates output pulse


    OCR Scan     		PDF GD54/74LS123 10OOpF, 402A7S7

    Untitled

    Abstract: No abstract text available
    Text: GD54/74LS125A QUADRUPLE BUS BUFFER GATES W ITH 3-STATE OUTPUTS Description This device contains 4 buffers with 3-state out­ puts and is provided with an output control input C which is independent for each buffer. Pin Configuration Vcc 4C 4A 4Y 3C 3A 3Y 14


    OCR Scan     		PDF GD54/74LS125A

    74ls123n

    Abstract: 038L 74LS123M M74LS123N
    Text: I R C H I L D S E M I C O N D U C T O R TM • R etriggerable to 100% duty cycle General Description The D M 74LS123 is a dual retriggerable m onostable m ultivi­ brator capable of generating output pulses from a few nano-seconds to extrem ely long duration up to 100% duty


    OCR Scan     		PDF DM74LS123 DM74LS123 74LS123 74ls123n 038L 74LS123M M74LS123N

    CI 7408

    Abstract: CI 74LS08 TTL 74ls21 74LS21 7407 connection diagram 54LS CI 7413 7432 TTL fairchild 74LS125 7408 and
    Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS D IG IT A L - T T L D65 54/7413, 54LS/74LS13 Vcc NC R R R fü| FÖI f71 r«l D66 54/74125, 54LS/74LS125 D67 54/74126, 54LS/74LS126 Vcc Vcc äJ QND E D68 54LS/74LS365 j y E D O 3X 5 rn m D O E D D O E D O IPTJ? ~ ? f i r


    OCR Scan     		PDF 54LS/74LS13 54LS/74LS125 54LS/74LS126 54LS/74LS365 54LS/74LS366 54LS/74LS367 54LS/74LS368 I4S09 54LS/74LS11 54H/74H11 CI 7408 CI 74LS08 TTL 74ls21 74LS21 7407 connection diagram 54LS CI 7413 7432 TTL fairchild 74LS125 7408 and

    54LS124

    Abstract: 74LS124 DM74LS124 LS124 "Voltage Controlled Oscillators" DM54 DM74 dm54ls12
    Text: % MSI DM 54/DM 74LS124 Dual Voltage Controlled Oscillators General Description T h e enable input and the buffered o u tp u t operate at standard Schottky-clam ped T T L levels. The enable input is one standard load in each series. A lth o u g h these devices can operate fro m a single 5-volt supply, separate


    OCR Scan     		PDF DM54/DM74LS124 DM54LS124/DM74LS124 54LS124 74LS124 DM74LS124 LS124 "Voltage Controlled Oscillators" DM54 DM74 dm54ls12

    74LS125A

    Abstract: LS125A
    Text: M O TO R O LA &> SN54/74LS125A SN54/74LS126A TRUTH TABLES LS125A INPUTS Î D L L L H H X LS126A IN P U T S E D H L H H L X OUTPUT L H I2I O UTPUT L H IZI QUAD 3-STATE BUFFERS LO W PO W ER SC H O T T K Y L “ LOW Voltage Level H « HIGH Voltage Level X * Don't Care


    OCR Scan     		PDF LS125A SN54/74LS125A SN54/74LS126A LS126A LS126A LS125A 74LS125A

    LS126A

    Abstract: LS125A ttl 493 LSI25A
    Text: MOTOROLA SN54LS/74LS125A SN54LS/74LS126A TRU TH TABLES LS125A INPUTS LS126A IN P U T S E H L H H L X O UTP UT E D L L L L H H H X 21 OUTPUT L H (2 QUAD 3-STATE BUFFERS LOW POW ER S C H O TTK Y L 31 LOW Voltage Level H = H IG H V oltage Level X * D o n 't Care


    OCR Scan     		PDF SN54LS/74LS125A SN54LS/74LS126A LS126A LS126A LS125A ttl 493 LSI25A

    74LS126AP

    Abstract: No abstract text available
    Text: MITSUBISHI LSTTLs M 74LS126AP Q U AD R U PLE BU S BU FFER G A TE WITH 3-STA TE O UTPUT DESCRIPTION PIN CONFIGURATION TOP VIEW The M 74LS126AP is a semiconductor integrated circuit containing 4 buffers w ith 3-state outputs and is provided w ith an o u tp u t control in p u t OC which is independent fo r


    OCR Scan     		PDF 74LS126AP 74LS126AP 500ns, b2LHfl27 0013Sbl 14-PIN 16-PIN 20-PIN

    74LS123A

    Abstract: CY323 74123 74LS123 monostable multivibrator using 74123 S54123F 74122 74122 Retriggerable Monostable Multivibrator 74123 time delay S54123
    Text: 5 4 /7 4 1 2 3 54LS/74LS123A Prelim inary DESCRIPTION PIN CONFIGURATIONS data FEATURES These r e tr ig g e r a b le m o n o s ta b le m u ltiv ib ra to rs fe a tu re d c trig g e rin g fro m g a t­ ed a c tiv e LO W in p u ts (A ) a nd a c tiv e HIGH in p u ts (B ) a nd a ls o p ro v id e o v e rrid in g d ire c t


    OCR Scan     		PDF 54LS/74LS123A 54H/74H, 54S/74S 54LS/74LS 54S/74S; 54LS/74LS 74LS123A CY323 74123 74LS123 monostable multivibrator using 74123 S54123F 74122 74122 Retriggerable Monostable Multivibrator 74123 time delay S54123

    74ls gate symbols

    Abstract: TTL 74ls125 74125 ic 74LS125 74125 logic diagram 74LS series logic gate symbols 74125 TTL 74ls126 74LS366 TTL 74126
    Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -T T L D65 54/7413, 54LS/74LS13 Vcc NC R R R fü| FÖI f71 r«l D66 54/74125, 54LS/74LS125 D67 54/74126, 54LS/74LS126 Vcc Vcc EEp ^ ] III III liJ Lil 111 Lil 111 QND y y O E D O rn m E D O E D O R R R R Fol R |7|


    OCR Scan     		PDF 54LS/74LS13 54LS/74LS125 54LS/74LS126 54LS/74LS365 54LS/74LS366 54LS/74LS367 54LS/74LS368 54LS/74LS125 54LS/74LS126 74ls gate symbols TTL 74ls125 74125 ic 74LS125 74125 logic diagram 74LS series logic gate symbols 74125 TTL 74ls126 74LS366 TTL 74126

    74LS123A

    Abstract: CY323 74ls123an
    Text: 5 4 /7 4 1 2 3 54LS/74LS123A Preliminary data DESCRIPTION PIN CONFIGURATIONS FEATURES These r e t r ig g e r a b le m o n o s ta b le m ultivibrators feature d c triggering from g a t­ ed active LOW inputs (A) and active HIGH inputs (B) and also provide overriding dire ct


    OCR Scan     		PDF 54LS/74LS123A 74LS123A CY323 74ls123an

    M74LS123P

    Abstract: jtw 07 DIODE 20-PIN
    Text: MITSUBISHI LSTTLs M 74LS123P DUAL R E T R IG G ER A B LE M ONOSTABLE M ULTIVIBRATO R WITH R E S E T DESCRIPTION The 74LS123P is a semiconductor integrated circu it containing tw o retriggerable monostable m u ltivib ra to r cir­ cuits w ith direct reset inputs.


    OCR Scan     		PDF M74LS123P M74LS123P 16-PIN 20-PIN jtw 07 DIODE