SO-140

Abstract: DN74LS12
Contextual Info: DN74LS1 2 LS TTL DN74LS Series DN74LS12 T rip le 3 - input P o sitiv e NAND G ates with Open C ollector Outputs • Description P-1 DN 74LS12 contains three 3-input positive isolation NAND gate circuits w ith open collector outputs. ■ Features • •

DN74LS193

Contextual Info: DN74LS193 LS T T L DN74LS Series D 7 N 4 L S 1 9 3 Synchronous 4 - b it Binary U p /D o w n Dual Clock Counters with R eset • Description P-2 D N 7 4 LS 1 9 3 is a synchronous hexadecim al (4-bit b in ary) up/down counter w ith direct-coupled reset input and set

DN74LS125A

Abstract: MA161
Contextual Info: I LS TTL DN74LS Series DN74LS125A DN74LS125A Quad Bus Buffer Gates with 3 -sta te Outputs • Description P-1 DN 74LS125A contains four 3-state o u tp u t b uffer gate circuits, each w ith independent o u tp u t-co n tro l input-C term inals. ■ Features

DN74LS145

Contextual Info: LS TTL DN74LS Series DN74LS145 DN74LS145 iv ^ L S ^ BCD to Decimal Decoders / Drivers P-2 • Description DN 74LS145 is a BCD to decim al decoder/ driver w ith open collector o u tp u ts. ■ Features • • • • Large o u tp u t cu rrent I o l ^ 80m A m axim um )

DN74LS194A

Abstract: MA161
Contextual Info: ! LS TTL DN74LS Series DN74LS194A DN74LS194A 4 -b it Bidirectional Universal Shift R egisters • Description P-2 DN 74LS194A is a bidirectional 4-bit serial/parallel input to serial/parallel output shift register. ■ • • • • • • Features Synchronous serial/parallel input to serial/parallel output

DN74LS138

Abstract: DN74LS139
Contextual Info: LS TTL DN74LS Series DN74LS138 DN74LS138 3 -lin e to 8 -lin e Decoders / Demultiplexers • Description P-2 DN74LS138 is a 3-bit decimal to octal decoder/demulti­ plexer with enable inputs. Features Three types of enable inputs Quaternary to hexadecimal decoder/demultiplexer capa­

TTL Schmitt-Trigger Inverters

Abstract: DN74LS14
Contextual Info: I* DN74LS14 L S T T L DN74LS Series D N 7 4 L S 1 4 Hex S ch m itt-T rigger Inverters • D e scrip tion D N 74S14 contains six inverter circuits w ith Schm itt triggers. ■ Features • • • • Ideal for w aveform shaping Low pow er consum ption P j = 50mW typical

DN74LS10

Abstract: MA161
Contextual Info: I LS TTL DN74LS Series DN74LS10 DN74LS10 T riple 3 - input P o sitiv e NAND Gates • Description D N 74LS10 contains three 3-input positive isolation NAND gate circuits. ■ Features • • • • Low pow er consum ption P,j = 6mW typical High speed ( tpd = 10ns typical)

TJ4D

Abstract: DN74LS173 MA161
Contextual Info: I DN74LS173 LS TTL DN74LS Series DN74LS173 4 -b it D-type R egisters with 3 -state Outputs P-2 • Description DN74LS173 is a 4-bit register with 3-state outputs. ■ Features • Capability for data holding irrespective o f clock pulse number • Data nondestructive during 3-state output

Diode RL 4B

Abstract: DN74LS158 MA161
Contextual Info: LS TTL DN74LS Series DN74LS158 DN74LS158 Quad 2 -lin e to 1 -lin e Data S electors / Multiplexers • Description P -2 D N 74LS158 contains four 2-line to 1-line data selector/ m ultiplexer circuits. ■ Features • • • • • Inverted o u tp u t C om m on enable in p u t for all fo u r circuits

DN74LS162A

Abstract: MA161
Contextual Info: LS TTL DN74LS Series DN74LS162A DN74LS162A Synchronous Decade Counters • Description DN74LS162A is a settable synchronous decade counter with synchronous reset input. ■ • • • • P-2 Features Synchronous reset and set inputs Carry output and enable input for cascade connection

sr flip flop

Abstract: DN74LS113 MA161
Contextual Info: DN74LS113 LS TTL DN74LS Series D N 7 4 L S 1 1 3 ^ 7 ^ U S 3 Dual J-K Negative Edge-Triggered F lip -F lo p s with Set) • Description P-l D N74LS113 contains tw o negative-edge triggered J-K flip­ flop circuits, each w ith independent clock-CP, J, K, and

DN74LS109

Abstract: MA161 j-k flip flop clock toggle
Contextual Info: LS TTL DN74LS Series DN74LS109 DN74LS109 J07 Dual J-K P ositive Edge-Triggered F lip-F lops with S et and Reset • Description P -2 D N 7 4 L S 1 0 9 c o n ta in s tw o p o sitive-edge trig g ered J-K flip ­ flo p c irc u its, each w ith in d e p e n d e n t clock-C P, J, K , and

DN74LS175

Contextual Info: LS TTL DN74LS Series DN74LS175 DN74LS175 'V74LS175T Quad D-type F lip -F lop s with Reset • Description DN74LS175 contains four positive-edge triggered D-type flip-flop circuits with common clock-CP and direct-coupled reset inputs, and independent data-D inputs.

DN74LS174

Contextual Info: ! DN74LS174 LS TTL DN74LS Series DN74LS174 Hex D-type F lip Flops with Reset • Description DN74LS174 contains six positive-edge triggered D-type flip-flop circuits with common clock-CP and direct-coupled reset inputs, and independent data-D inputs. P-2

DN74LS10

Abstract: MA161
Contextual Info: LS TTL DN74LS Series DN74LS10 DN74LS10 bio74-LSto T riple 3 - input P o sitiv e NAND Gates • Description D N 74LS10 contains three 3-input positive isolation NAND gate circuits. ■ Features • • • • Low pow er consum ption Pd = 6mW typical High speed ( tpd = 10ns typical)

Contextual Info: LS TTL DN74LS Series DN74LS125A DN74LS125A > IS a s A Quad Bus Buffer Gates with 3 -sta te Outputs • Description P-1 D N 74LS125A c o n ta in s c irc u its , each te rm in a ls. w ith f o u r 3 -sta te in d e p e n d e n t o u tp u t b u ff e r gate o u tp u t- c o n tr o l

Contextual Info: L S T T L DN74LS Series DN74LS14 DN74LS14 I Ki 74 LS Hex Schm itt-Trigger Inverters • Description P-1 D N 7 4 S 1 4 c o n ta in s six in v e rte r c irc u its w ith S c h m itt triggers. ■ Features • Id eal fo r w av efo rm sh ap in g • L ow p o w e r c o n s u m p tio n P d = 50m W ty p ic a l)

Contextual Info: DN74LS136 LS TTL DN74LS Series DN74LS136 Quad 2 - input E xclusive OR G ates with Open C ollector Outputs • Description P-1 DN 74LS136 contains four 2-input exclusive OR gate circuits w ith open collector outputs. ■ • • • • Features “Wired” AND capability

Contextual Info: LS TTL DN74LS Series DN74LS139 DN74LS139 Dual 2 -lin e to 4 -lin e Decoders / Demultiplexers H Description P -2 D N 74LS139 contains tw o 2-bit binary to quaternary de­ coder/dem ultiplexer circuits, each w ith independent enable input term inals. • Features

Contextual Info: LS TTL DN74LS Series DN74LS11 DN74LS11 D^74LS11 Triple 3-input P ositive AND Gates • Description P-1 D N 74L S 11 contains three 3-input positive isolation AND gate circuits. I Features • Low pow er consum ption P d = 13mW typical • High speed ( t pii = 9ns typical)

Contextual Info: LS TTL DN74LS Series DN74LS158 DN74LS158 Quad 2 -lin e to 1-line Data Selectors / Multiplexers • Description P -2 DN74LS158 contains four 2-line to 1-line data selector/ multiplexer circuits. ■ Features • • • • • Inverted output Common enable input for all four circuits

Contextual Info: LS TTL DN74LS Series DN74LS157 D N 7 4 L S 1 5 7 Quad 2 -line to 1-lin e Data S electo rs/ Multiplexers • Description P-2 DN74LS157 contains four 2-line to 1-line data selector/ multiplexer circuits. ■ Features • Common enable input for all four circuits

Contextual Info: I LS TTL DN74LS Series DN74LS113 DN74LS113 Dual J-K Negative Edge-Triggered Flip-Flops with Set I Description P-1 DN74LS113 contains two negative-edge triggered J-K flipflop circuits, each with independent clock-CP, J, K, and direct-coupled set input terminals.