octal Bilateral Switches
Abstract: MM74HC14M MM74HC138M CD4025BCM MM74HC00M MM74HC74AM MM74HC125M MM74HC04M cd4046bcm cd4052bcm
Text: 1/3 CMOS LOGIC MM74HC SERIES MM74HCT/U SERIES • HIGH SPEED CMOS TECHNOLOGY, CMOS DRIVE LEVELS, SPEED COMPARABLE TO 74LS SERIES Part Number Description • HIGH SPEED CMOS TECHNOLOGY, TTL DRIVE LEVELS, SPEED COMPARABLE TO 74LS SERIES SQP £ ea. Gates & Inverters
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MM74HC
MM74HC00M
MM74HC02M
MM74HC04M
MM74HC08M
MM74HC14M
MM74HC32M
MM74HC86M
MM74HC132M
MM74HC74AM
octal Bilateral Switches
MM74HC138M
CD4025BCM
MM74HC125M
cd4046bcm
cd4052bcm
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74LS18P
Abstract: No abstract text available
Text: MITSUBISHI LSTTLs M 74LS 18P DUAL 4-IN P U T NAND SCHMITT TRIGGER DESCRIPTION The M 74LS 18P is a semiconductor integrated circuit PIN CONFIGURATION TOP VIEW containing tw o 4-input positive-logic N A N D gates having a schm itt trigger function and negative-logic N O R gates.
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500ns,
b2LHfl27
0013Sbl
74LS18P
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IC 74LS14
Abstract: 74ls14 74LSxx ic 74ls13
Text: M OTOROLA SN54/74LS13 SN54/74LS14 SCHMITT TRIGGERS DUAL GATE/HEX INVERTER The S N 54LS /74LS 13 and SN 54LS /74LS 14 contain logic gates/inverters which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into
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/74LS
SN54/74LS13
SN54/74LS14
IC 74LS14
74ls14
74LSxx
ic 74ls13
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74LS14 not gate
Abstract: 74LS14 74ls14 ttl ttl 74ls14 74LS14 DATA LS14 74LS13 TTL Schmitt-Trigger Inverters 751A-02 LS13
Text: MOTOROLA SN54/74LS13 SN54/74LS14 SCHMITT TRIGGERS DUAL GATE/HEX INVERTER The SN 54LS /74LS 13 and S N 54LS /74LS 14 contain logic gates/inverters which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into
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SN54LS/74LS13
SN54LS/74LS14
SN54/74LS13
SN54/74LS14
74LS14 not gate
74LS14
74ls14 ttl
ttl 74ls14
74LS14 DATA
LS14
74LS13
TTL Schmitt-Trigger Inverters
751A-02
LS13
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74ls48 PIN OUT
Abstract: No abstract text available
Text: <8> M OTOROLA D E S C R IP T IO N — The S N 54LS /74LS 48 and S N 54LS /74LS 49 are BCD to 7-Segm ent Decoders consisting of NAND gates, input buffers and seven AND-OR-INVERT gates. The LS49 offers active HIGH opencollector outputs for current-sourcing applications to drive logic circuits
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/74LS
74ls48 PIN OUT
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HCTLS266
Abstract: 74HCTLS
Text: Zvtrex ZX54HCTLS ZX74HCTLS 266 Quad Exdusive-NOR Gates with Open-Drain Outputs February 1985 OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family These devices contain four independent exclusive-NOR
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ZX54HCTLS
ZX74HCTLS
54/74LS
74HCTLS:
54HCTLS:
HCTLS266
74HCTLS
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74hctls
Abstract: No abstract text available
Text: Zytrex_ sags12 Triple 3-Input NAND Gates with Open-Drain Outputs February 1985 OBJECTIVE SPECIFICATIONS Features Description • Function, pin*out, speed and drive compatibility with 54/74LS logic family These devices contain three independent 3-input NAND
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ZX54HCTLS
ZX74HCTLS
54/74LS
74HCTLS:
54HCTLS:
74hctls
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Altera EP1800
Abstract: EP1800 JEDEC FORMAT EP1800 altera logicaps TTL library SCHEMA PA BUILT UP EP1800 LOGIC DIAGRAM ep18001
Text: EP1800 Erasable, User-Configurable LSI circuit capable of implementing 2100 equivalent gates of conventional and custom logic. Speed equivalent to 74LS TTL with 25 MHz clock rates. “Zero Power” typically 10/jA standby . Active power of 250 mW at 5 MHz.
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EP1800
Altera EP1800
EP1800 JEDEC FORMAT
EP1800
altera logicaps TTL library
SCHEMA PA BUILT UP
EP1800 LOGIC DIAGRAM
ep18001
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Dual 4-input NAND Schmitt Trigger
Abstract: M74LS13P M74ls14p 20-PIN
Text: MITSUBISHI LSTTLs M74LS13P DUAL 4 -IN P U T NAND S C H M ITT TRIGGER DESCRIPTION The M 74LS 13P PIN CONFIGURATION TOP VIEW is a semiconductor integrated circuit containing tw o 4-inp ut positive-logic N A N D gates having a Schm itt trigger function and negative-logic NOR gates.
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M74LS13P
M74LS13P
16-PIN
20-PIN
Dual 4-input NAND Schmitt Trigger
M74ls14p
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Untitled
Abstract: No abstract text available
Text: MITSUBISHI LSTTLs M74LS13P DUAL 4 -IN P U T NAND S C H M ITT TRIGGER DESCRIPTION The M 74LS 13P PIN CONFIGURATION TOP VIEW is a semiconductor integrated circuit containing tw o 4-inp ut positive-logic N A N D gates having a Schm itt trigger function and negative-logic NOR gates.
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M74LS13P
b2LHfl27
0013Sbl
14-PIN
16-PIN
20-PIN
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Zytrex OR gate
Abstract: 74HCTLS
Text: Z v t r e ZX54HCTLS ZX74HCTLS x Quad 2-Input Exclusive-OR Gates February 1985 OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family These devices contain four independent 2-input Exclu
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54/74LS
74HCTLS:
54HCTLS:
ZX54HCTLS
ZX74HCTLS
Zytrex OR gate
74HCTLS
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7427 pin configuration
Abstract: TTL 7427 74ls gate symbols 7427 1N3064 1N916 74LS 74LS27 LS27 N7427N
Text: Signetics I 7427, LS27 Gates Triple Three-Input NOR Gate Product Specification Logic Products TYPE TYPICAL SUPPLY CURRENT TOTAL TYPICAL PROPAGATION DELAY 7427 9ns 13m A 74LS 27 10ns 2.7m A ORDERING CODE COMMERCIAL RANGE Vcc = 5V ±5% ; Ta = 0°C t o + 70°C
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74LS27
N7427N,
N74LS27N
N74LS27D
10LSul
7427 pin configuration
TTL 7427
74ls gate symbols
7427
1N3064
1N916
74LS
LS27
N7427N
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74hctls
Abstract: No abstract text available
Text: Zyfrex ZX54HCTLS M M m % ZX74HCTLS Quad 2-Input NAND Gates with Open-Drain Outputs February 1985 OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family These devices contain four independent 2-input NAND
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54/74LS
74HCTLS:
54HCTLS:
ZX54HCTLS
ZX74HCTLS
74hctls
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HCTLS
Abstract: 74hctls
Text: Z v t n ZX54HCTLS M ZX74HCTLS x February 1985 Quad 2-Input AND Gates with Open-Drain Outputs OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family These devices contain four independent 2-Input AND
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ZX54HCTLS
ZX74HCTLS
54/74LS
74HCTLS:
54HCTLS:
HCTLS
74hctls
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shiftregisters
Abstract: EP910 altera TTL library 74LS series logic gates 74LS EP1810 EP1810-45 EP610 PLE40 altera logicaps TTL library
Text: EP1810 Y 7 \ m HIGH PERFORMANCE 4 8 MACROCELL EPLD m 10 I U FEATURES GENERAL DESCRIPTION • Erasable, User-Configurable LSI circuit capable of implementing 2100 equivalent gates of conven tional and custom logic. • Speed equivalent to 74LS TTL with 33 MHz clock
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KS74HCT
Abstract: DEJJ
Text: SAMSUNG SEMICONDUCTOR INC D2 KS54HCTLS M KS74HCTLS DEJJ T l t m M S U00bE7fl 1 | T'H3»Zj Quad 2-Input NOR Gates FEATURES DESCRIPTION • Function, pln-out, speed and drive compatibility with 54/74LS logic family • Low power consumption characteristic of CMOS
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U00bE7fl
KS54HCTLS
KS74HCTLS
54/74LS
KS74HCTLS:
KS54HCTLS:
300-mil
7Tb414S
90-XO
14-Pin
KS74HCT
DEJJ
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74LS00P
Abstract: M74LS00P
Text: M IT S U B IS H I LSTTLs M74LS00P QUADRUPLE 2-IN P U T POSITIVE NAND GATES DESCRIPTION The M 74LS 00P is semiconductor integrated circuit contain ing fo u r dual-input positive-logic N A N D gates, usable as negative-logic N O R gates. FEATURES • High breakdown input voltage V | S 15 V
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M74LS00P
0013Sbl
14-PIN
16-PIN
20-PIN
74LS00P
M74LS00P
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74hctls
Abstract: No abstract text available
Text: Zytrex_ æ&OO Quad 2-Input NAND Gates February 1965 OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family These devices contain four independent 2-input NAND gatesJhat perform the Boolean functions Y = A • B or
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54/74LS
74HCTLS:
54HCTLS:
ZX74HCTLS
74hctls
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M74LS00P
Abstract: 20-PIN M74LS00
Text: M IT S U B IS H I LSTTLs M74LS00P QUADRUPLE 2-IN P U T POSITIVE NAND GATES DESCRIPTION The M 74LS 00P is semiconductor integrated circuit contain ing fo u r dual-input positive-logic N A N D gates, usable as negative-logic N O R gates. FEATURES • High breakdown input voltage V | S 15 V
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M74LS00P
M74LS00P
16-PIN
20-PIN
M74LS00
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74HCTLS
Abstract: No abstract text available
Text: Zytrex ZXS4HCTLS ZX74HCTLS February 1985 11 Triple 3-Input AND Gates O BJECTIVE S P E C IF IC A TIO N S Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family These devices contain three independent 3-input AND
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54/74LS
74HCTLS:
54HCTLS:
ZX54HCTLS
ZX74HCTLS
74HCTLS
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TTL 7411
Abstract: TTL 7410 PIN CONFIGURATION 7410 PIN CONFIGURATION 7411 74LS10 pin configuration 7410 pin configuration 74LS10 function table 7411 ttl pin configuration of 7410 LS 7411
Text: Signetics I 74-10, 7411, LS10, LS11, S10, S11 Gates Logic Products Triple Three-Input NAND '10 , AND ('11) Gates Product Specification • TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT (TOTAL) 7410 9ns 6m A 74LS 10 10ns 1.2m A 74S 10 3ns 12m A 7411
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74LS10
74S10
74LS11
74S11
N7410N,
N74LS10N,
N74S10N
N7411N,
N74LS11N,
N74S11N
TTL 7411
TTL 7410
PIN CONFIGURATION 7410
PIN CONFIGURATION 7411
74LS10 pin configuration
7410 pin configuration
74LS10 function table
7411 ttl
pin configuration of 7410
LS 7411
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hctls86
Abstract: No abstract text available
Text: SAMSUNG SEMICONDUCTOR INC OB DE^ 7 H m M a K S S 4 H C T L S O ^ . KS74HCTLS 000^330 7 '7_" - ^ 3 -v2 Quad 2-Input Exclusive-OR Gates FEATURES DESCRIPTION • Function, pin-out, speed and drive compatibility with 54/74LS logic family
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KS74HCTLS
54/74LS
KS74HCTLS:
KS54HCTLS:
300-mil
7Tb414S
90-XO
14-Pin
hctls86
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74HCTLS
Abstract: No abstract text available
Text: Z v t r e ZXS4HCTLS M M g ZX74HCTLS § x Quad 2-Input NAND Gates with Opert-Drain Outputs February 1985 OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74LS logic family These devices contain four independent 2-input NAND
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54/74LS
74HCTLS:
54HCTLS:
ZX74HCTLS
74HCTLS
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Zytrex quad and gate
Abstract: 74hctls
Text: Z y tr c x _ February1985 08 Quad 2-Input AND Gâté# / OBJECTIVE SPECIFICATIONS Features Description • Function, pln-out, speed and drive compatibility with 54/74LS logic family These devices contain four independent 2-input AND gates. They perform the Boolean functions Y = A • B or
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ZX54HCTLS
ZX74HCTLS
54/74LS
74HCTLS:
54HCTLS:
Zytrex quad and gate
74hctls
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