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onsemi 74F114PC IC FF JK TYPE DUAL 1BIT 14DIP
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DigiKey	74F114PC	Tube			25	1 - 10 - 100 $0.472 1000 $0.472 10000 $0.472	Buy Now
Fairchild Semiconductor Corporation 74F114PCQR IC,FLIP-FLOP,DUAL,J/K TYPE,F-TTL,DIP,14PIN,PLASTIC
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Quest Components	74F114PCQR		25			1 - 10 - 100 - 1000 - 10000 -	Buy Now
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Chip 1 Exchange	74F114PC		340			1 - 10 - 100 - 1000 - 10000 -	Get Quote

74F114PC Datasheets (5)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
74F114PC		Fairchild Semiconductor	Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears		Original	PDF
74F114PC		National Semiconductor	Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears		Original	PDF
74F114PC		Unknown	Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.		Historical	PDF
74F114PCQR		Unknown	Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.		Historical	PDF
74F114PCX		Fairchild Semiconductor	Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears		Original	PDF

74F114PC Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
jk flip flop Abstract: 74F114 74F114PC 74F114SC C1995 F114 M14A N14A Text: 74F114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears General Description The ’F114 contains two high-speed JK flip-flops with common Clock and Clear inputs Synchronous state changes are initiated by the falling edge of the clock Triggering occurs at a voltage level of the clock and is not directly related	Original	74F114 jk flip flop 74F114 74F114PC 74F114SC C1995 F114 M14A N14A	PDF
74F114 Abstract: 74F114PC 74F114SC M14A MS-001 N14A Text: Revised August 1999 74F114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears General Description The 74F114 contains two high-speed JK flip-flops with common Clock and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not	Original	74F114 74F114 74F114PC 74F114SC M14A MS-001 N14A	PDF
74F114 Abstract: 74F114PC 74F114SC F114 M14A N14A Text: 74F114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears General Description The ’F114 contains two high-speed JK flip-flops with common Clock and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at	Original	74F114 74F114 74F114PC 74F114SC F114 M14A N14A	PDF
220v AC voltage stabilizer schematic diagram Abstract: BA 49182 RJh 3047 rjh 3047 equivalent a1458 opto philips ecg master replacement guide MOSFET, rjh 3077 sc1097 philips ecg semiconductors master replacement guide Electronic ballast 40W using 13005 transistor Text: QUICK INDEX NEW IN THIS ISSUE! Detailed Index - See Pages 2-6 Fiber Optic Connectors and Accessories . . . . . . . . . . . See Page 121 Connectors, Cable Assemblies, IC Sockets . . . . . . . . . . . 10-122 Fiber Optic Cable, Connectors, and Accessories . . . . . . See Pages 118-122	Original	P390-ND P465-ND P466-ND P467-ND LNG901CF9 LNG992CFBW LNG901CFBW LNG91LCFBW 220v AC voltage stabilizer schematic diagram BA 49182 RJh 3047 rjh 3047 equivalent a1458 opto philips ecg master replacement guide MOSFET, rjh 3077 sc1097 philips ecg semiconductors master replacement guide Electronic ballast 40W using 13005 transistor	PDF
c5088 transistor Abstract: transistor C3207 TLO84CN sec c5088 IN5355B D2817A C3207 transistor toshiba f630 TLO81CP MC74HC533N Text: Transistor - Diode Cross Reference - H.P. Part Numbers to JEDEC Numbers Part Num. 1820-0225 1820-0240 1820-0352 1820-1804 1821-0001 1821-0002 1821-0006 1850-0062 1850-0064 1850-0075 1850-0076 1850-0093 1850-0099 1850-0126 1850-0137 1850-0150 1850-0151 1850-0154	Original	1853IMPATT c5088 transistor transistor C3207 TLO84CN sec c5088 IN5355B D2817A C3207 transistor toshiba f630 TLO81CP MC74HC533N	PDF
74F161 PC Abstract: 74F163PC 74f500 74f558 74F164PC 74F548PC 74F138d 74F547PC transistor f630 74F253DC Text: F a ir c h ild A d v a n c e d S c h o t t k y T L $ 3. HANDLING PRECAUTIONS FOR SEMICONDUCTOR COMPONENTS The follow ing handling precautions should be observed for oxide isolation, shallow junction processed parts, such as FAST or 100K ECL: 1. All Fairchild devices are shipped in conducting foam or anti	OCR Scan		PDF
Untitled Abstract: No abstract text available Text: E M IC O N D U C T O R T 74F114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears General Description A synchronous Inputs: The ’F114 contains tw o high-speed JK flip-flops with com mon C lock and C lear inputs. Synchronous state changes are	OCR Scan	74F114	PDF
Untitled Abstract: No abstract text available Text: National Semiconductor 74F114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears General Description The ’F114 contains two high-speed JK flip-flops with com mon Clock and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering oc	OCR Scan	74F114	PDF
D406 Abstract: 74F114 74F114PC 74F114SC F114 M14A N14A Text: S E M IC O N D U C T O R tm 74F114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears A synchronous Inputs: General Description The ’F114 contains tw o high-speed JK flip-flops w ith com mon Clock and C lear inputs. Synchronous state changes are	OCR Scan	74F114 D406 74F114 74F114PC 74F114SC F114 M14A N14A	PDF
Untitled Abstract: No abstract text available Text: p P r iM 9 H 8 ! ! iQ Q Q Revised A ugust 1999 EMICONDUCTGRTM 74F114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears General Description S im ultaneous LO W signals on S q and C q force both Q and The 74F114 contains tw o high-speed JK flip-flops with	OCR Scan	74F114	PDF
Untitled Abstract: No abstract text available Text: August 1995 74F114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears General Description The ’F114 contains two high-speed JK flip-flops with com mon Clock and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering oc	OCR Scan	74F114	PDF
Untitled Abstract: No abstract text available Text: National Semiconductor 74F114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears General Description The 'F114 contains two high-speed JK flip-flops with com mon Clock and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering oc	OCR Scan	74F114	PDF