74F51 Search Results

02P35

Abstract: 74F519 74F518
Contextual Info: SN 54F518, SN 54F519, SN 74F518, SN 74F519 BIT IDENTITY COM PARATO RS WITH OPEN-COLLECTOR OUTPUTS 0 2 9 3 2 . MARCH 1987 • SN&4F518, SN 54F519 . . . J PACKAGE S N 74F518, SN 74F519 . . . DW OR N PACKAGE Compares Two 8-Bit Words 'F518 Has 20-kft Pull-up Resistors on Q

74F51

Abstract: 74F51PC 74F51SC 74F51SJ M14A M14D N14A
Contextual Info: 74F51 Dual 2-Wide 2-Input; 2-Wide 3-Input AND-OR-Invert Gate 3-3 AND-OR-INVERT function. General Description This device contains two independent logic units, one performing a 2-2 AND-OR-INVERT and the other performing a Ordering Code: Commercial Package Number

Contextual Info: Revised Ju ly 1999 S E M IC O N D U C T O R ! TM 74F51 Dual 2-Wide 2-Input; 2-Wide 3-Input AND-OR-lnvert Gate General Description This device contains tw o independent logic units, one per­ form ing a 2-2 AN D -O R -IN V E R T and the o ther perform ing a

74F51

Abstract: 74F51PC 74F51SC 74F51SJ M14A M14D MS-001 N14A
Contextual Info: Revised July 1999 S E M I C O N D U C T O R TM 74F51 Dual 2-Wide 2-Input; 2-Wide 3-Input AND-OR-lnvert Gate General Description This device contains tw o independent logic units, one per­ form ing a 2-2 A N D -O R -IN VER T and the other perform ing a 3-3 A N D -O R -IN VER T function.

Contextual Info: National ÆM Semiconductor 54F/74F51 2-2-2-3 AND-OR-lnvert Gate General Description This device contains tw o independent logic units, one per­ form ing a 2-2 A N D -O R -IN VER T and th e o ther perform ing a 3-3 A N D -O R -IN VER T function. Ordering Code:

Contextual Info: M M O T O R O L A Advance Information M C 54F/74F51 D ual 2-W ide 2-Input, 2-W ide 3-Input A N D -O R-lnvert Gate LOGIC SYMBOL FAST " Schottky TTL 1 u 12 13 9 10 11 FU N C T IO N A L TA B LES For 3-Input Gates For 2-Input Gates Inputs Output Inputs Output

N74F51D

Abstract: 74F51 N74F51N
Contextual Info: Philips Semiconductors FAST Products Product specification Dual 2-wide 2-input, 2-wide 3-input AND-OR-invert gate TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT TOTAL 74F51 3.0ns 3.5mA PIN CONFIGURATION D0a 1 14 VCC D1a 2 13 D0c D1b 3 12 D0b D1c 4

74F51

Abstract: 74F51PC 74F51SC 74F51SJ M14A M14D MS-001 N14A
Contextual Info: Revised September 2000 74F51 Dual 2-Wide 2-Input; 2-Wide 3-Input AND-OR-Invert Gate General Description This device contains two independent logic units, one performing a 2-2 AND-OR-INVERT and the other performing a 3-3 AND-OR-INVERT function. Ordering Code:

schmitt trigger non inverting

Abstract: 74F864 3 bit magnitude comparator 74F154 74F579 74F5300 equivalent multiplexer 30 pin QUAD D FLIP-FLOP "FAST TTL" 74*545
Contextual Info: Philips Semiconductors Section 2 FAST TTL Logic Devices FAST TTL Logic Series CONTENTS 74F00 74F02 74F04 74F06 74F06A 74F07 74F07A 74F08 74F10 74F11 74F14 74F20 74F27 74F30 74F32 74F37 74F38 74F51 74F64 74F74 74F85 74F86 74F109 74F112 74F113 74F125 74F126

Contextual Info: IO & National Semiconductor 74F51 2-2-2-3 AND-OR-lnvert Gate General Description This device contains two independent logic units, one per­ forming a 2-2 AND-OR-INVERT and the other performing a 3-3 AND-OR-INVERT function. Ordering Code: s e e section n Commercial

2-input & 3-input AND-OR-invert Gate

Abstract: 74F51 N74F51D N74F51N
Contextual Info: INTEGRATED CIRCUITS 74F51 Dual 2-wide 2-input, 2-wise 3-input AND-OR-invert gate Product specification IC15 Data Handbook Philips Semiconductors 1989 Mar 03 Philips Semiconductors Product specification Dual 2-wide 2-input, 2-wide 3-input AND-OR-invert gate

Contextual Info: Philips Semiconducfors-Slgnetlcs _ _ _ _ FAST 74F51 G ot Document No. 853-0054 ECN No. 95962 Date of issue March 3,1989 Status Product Sped ficaSion Dual 2-Wide 2-lnput, 2-Wide 3-lnput AND-OR-Invert G ate FAST Products TYPICAL SUPPLY CURRENT TOTAL

74F51

Abstract: 74F51PC 74F51SC 74F51SJ M14A M14D MS-001 N14A
Contextual Info: Revised July 1999 74F51 Dual 2-Wide 2-Input; 2-Wide 3-Input AND-OR-Invert Gate General Description This device contains two independent logic units, one performing a 2-2 AND-OR-INVERT and the other performing a 3-3 AND-OR-INVERT function. Ordering Code: Order Number

Contextual Info: C H IL D S E M I C O N D U C T O R TM 74F51 Dual 2-Wide 2-Input; 2-Wide 3-Input AND-OR-lnvert Gate General Description 3 3 a n d o r i n v e r t function. This device contains two independent logic units, one per­ forming a 2-2 AND-OR-INVERT and the other performing a

Contextual Info: MOTOROLA MC54/74F51 DUAL 2-WIDE 2-INPUT, 2-WIDE 3-INPUT AND-OR-INVERT GATE CONNECTION DIAGRAM Vqc 1C 1B 1F 1E 1D 1V PmI nil m rrn m in m DUAL 2-WIDE 2-INPUT, 2-WIDE 3-INPUT AND-OR-INVERT GATE FAST SCHOTTKY TTL □ J S U FFIX CE R A M IC C A SE 632-08 LU LU LU LU LU LU

Contextual Info: <8> MOTOROLA MC54/74F51 DUAL 2-WIDE 2-INPUT, 2-WIDE 3-INPUT AND-OR-INVERT GATE CONNECTION DIAGRAM Vqc 1C 1B 1F 1E 1D 1Ÿ DUAL 2-W ID E 2-INPUT, 2-W IDE 3-IN P U T A N D -O R -IN V E R T GATE FAST SCHOTTKY TTL J SUFFIX 1A 2A 2B 2C 2D 2Y C E R A M IC C A S E 632-08

Contextual Info: tß National Semiconductor 74F51 2-2-2-3 AND-OR-lnvert Gate General Description T his device co nta in s tw o ind ependent logic units, one per­ form ing a 2-2 A N D -O R -IN VER T and th e o th e r perform ing a 3-3 AN D -O R -IN V E R T function. Ordering Code:

Contextual Info: 531 National Jl Semiconductor 54F/74F51 2-2-2-3 AND-OR-lnvert Gate Ordering Code: See Section 5 Logic Symbol Connection Diagrams IEEE/IEC Pin Assignment for DIP, SOIC and Flatpak Pin Assignment for LCC and PCC a 1 A0 • B„- D, NC C, NC B, 00 0Ì0 C0 '

54F10

Abstract: 74F10
Contextual Info: NATIONAL SEMICOND -CLOGICJ I D E D | b S O l l S E - GObTOTM S | T -M 3-15 u> ZW A N a t io n a l ä im S e m ic o n d u c to r 54F/74F51 2-2-2-3 AND-OR-Invert Gate Ordering Code: seesection5 Logic Symbol Connection Diagrams IEEE/IEC Pin Assignment for LCC and PCC

Contextual Info: SNS4F51, 74F51 DUAL 2-WIDE 2 INPUT, 2-WIDE 3-INPUT AND-OR-INVERT GATES D3209, J A N U A R Y 1989 SN 54F51 . . . J PA C KA G E SN 74F51 . . . D OR N PACKAG E Package Options Include Plastic "Sm all Outline" Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil

751A-02

Abstract: MC54F51 MC74F51 MO-001 J21B
Contextual Info: Order this data sheet by M C54F51/D MOTOROLA SE M IC O N D U C TO R TECHNICAL DATA M C 54F 51 M C 74F51 Advance Information D u a l 2 -W id e 2 - ln p u t , 2 -W id e 3 - ln p u t A N D -O R - In v e r t G a te FAST S c h o ttk y TTL J SUFFIX CASE 632-07

751A-02

Abstract: H12Y 74f51
Contextual Info: MC54/74F51 DUAL 2-WIDE 2-INPUT, 2-WIDE 3-INPUT AND-OR-INVERT GATE CONNECTION DIAGRAM VCC 1C 1B 1F 1E 1D 1Y 14 13 12 11 10 9 8 DUAL 2-WIDE 2-INPUT, 2-WIDE 3-INPUT AND-OR-INVERT GATE FAST SCHOTTKY TTL 1 2 3 4 5 6 7 1A 2A 2B 2C 2D 2Y GND J SUFFIX CERAMIC CASE 632-08

Contextual Info: Philips Somlconductors-SlgneHcs Document No. 853-0054 ECNNo. 95962 Date of Issue March 3, 1989 Status Product Specification , _ _ , FAST 74F51 G ate Dual 2-Wide 2-Input, 2-Wide 3-Input AND-OR-lnvert Gate FAST Products TYPICAL PROPAGATION DELAY TYPE 74F51 TYPICAL SUPPLY CURRENT

74F51

Abstract: 74F51PC 74F51SC 74F51SJ C1995 M14A M14D N14A
Contextual Info: 74F51 2-2-2-3 AND-OR-Invert Gate General Description This device contains two independent logic units one performing a 2-2 AND-OR-INVERT and the other performing a 3-3 AND-OR-INVERT function Commercial Package Number Package Description 74F51PC N14A 14-Lead 0 300 Wide Molded Dual-In-Line