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    74ALS109A Search Results

    74ALS109A Result Highlights (3)

    Part ECAD Model Manufacturer Description Download Buy
    SN74ALS109AN Texas Instruments Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset 16-PDIP 0 to 70 Visit Texas Instruments Buy
    SN74ALS109AD Texas Instruments Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset 16-SOIC 0 to 70 Visit Texas Instruments
    SN74ALS109ANSR Texas Instruments Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset 16-SO 0 to 70 Visit Texas Instruments Buy
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    74ALS109A Price and Stock

    Rochester Electronics LLC SN74ALS109AN

    IC FF JK TYPE DUAL 1BIT 16DIP
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    Rochester Electronics LLC SN74ALS109ANS

    IC JK TYPE POS TRG DUAL 16SO
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    Texas Instruments SN74ALS109ANSR

    IC FF JK TYPE DUAL 1BIT 16SO
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    DigiKey SN74ALS109ANSR Cut Tape 1,980 1
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    Rochester Electronics SN74ALS109ANSR 12,000 1
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    Texas Instruments SN74ALS109AD

    IC FF JK TYPE DUAL 1BIT 16SOIC
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    DigiKey SN74ALS109AD Tube 1,024 1
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    Mouser Electronics SN74ALS109AD 363
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    Rochester Electronics SN74ALS109AD 5,270 1
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    Texas Instruments SN74ALS109AN

    IC FF JK TYPE DUAL 1BIT 16DIP
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    DigiKey SN74ALS109AN Tube 769 1
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    Mouser Electronics SN74ALS109AN 1,974
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    Bristol Electronics SN74ALS109AN 2,269
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    Rochester Electronics SN74ALS109AN 12,181 1
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    Chip 1 Exchange SN74ALS109AN 500
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    Component Electronics, Inc SN74ALS109AN 350
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    Find more 74ALS109A price and stock on Findchips.com

    74ALS109A Datasheets (8)

    Part ECAD Model Manufacturer Description Curated Type PDF
    74ALS109A Philips Semiconductors Dual J-K positive edge-triggered flip-flop with set and reset Original PDF
    74ALS109A Signetics Dual J-K positive edge-triggered flip-flop with set and reset Original PDF
    74ALS109AD Philips Semiconductors Dual J-K positive edge-triggered flip-flop with set and reset Original PDF
    74ALS109AD Signetics Dual J-K positive edge-triggered flip-flop with set and reset Original PDF
    74ALS109AD Signetics Dual J-KPosltlve Edge-Triggered Flip-Flops With Set and Reset Scan PDF
    74ALS109AN Philips Semiconductors Dual J-K positive edge-triggered flip-flop with set and reset Original PDF
    74ALS109AN Signetics Dual J-K positive edge-triggered flip-flop with set and reset Original PDF
    74ALS109AN Signetics Dual J-KPosltlve Edge-Triggered Flip-Flops With Set and Reset Scan PDF

    74ALS109A Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    74ALS

    Abstract: 74ALS109A 74ALS109AD 74ALS109AN SC00042
    Text: INTEGRATED CIRCUITS 74ALS109A Dual J-K positive edge-triggered flip-flop with set and reset Product specification IC05 Data Handbook Philips Semiconductors 1991 Feb 08 Philips Semiconductors Product specification Dual J-K positive edge triggered flip-flop


    Original     		PDF 74ALS109A 74ALS109A 74ALS 74ALS109AD 74ALS109AN SC00042

    Untitled

    Abstract: No abstract text available
    Text: Philips Sem iconductors Product specification 7A. Q1flQ. Dual J-K positive edge triggered flip-flop with set and reset PIN CONFIGURATION DESCRIPTION The 74ALS109A is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and


    OCR Scan     		PDF 74ALS109A

    1u9a

    Abstract: No abstract text available
    Text: Philips Semiconductors Product specification Dual J-K positive edge triggered flip-flop with set and reset DESCRIPTION PIN CONFIGURATION The 74ALS109A is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and


    OCR Scan     		PDF 74ALS109A 74ALS109A 74ALS 500ns SC00005 1u9a

    3rw 44

    Abstract: 74ALS109A 74ALS109AD 74ALS109AN SM15C
    Text: 7 4 A L S 109 A . FLIP-FLOP 74ALS109A Dual J-K>osltive Edge-Triggered Flip-Flops With Set and Reset Product Specification DESCRIPTION The 'ALS109A is a dual positive edge-triggered JK-type flip-flop featuring individual J, R, Clock, Set and Reset inputs; also true and complemen­


    OCR Scan     		PDF 74ALS109A ALS109A 74als 500ns 3rw 44 74ALS109AD 74ALS109AN SM15C

    TEXTOOL zif 40 pin socket

    Abstract: MS-012-AB 74ALS 74ALS109A 74ALS109AD 74ALS109AN SOL-24
    Text: 74ALS109A Signetics FLIP-FLOP 74ALS109A Dual J-K Positive Edge-Triggered Flip-Flops With Set and Reset ALS Products Product Specification DESCRIPTION TYPE The 'ALS109A is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, Clock, Set and Reset inputs; also true and complemen­


    OCR Scan     		PDF 74ALS109A ALS109A 5M-1982. eounterdock-22) TEXTOOL zif 40 pin socket MS-012-AB 74ALS 74ALS109A 74ALS109AD 74ALS109AN SOL-24

    Untitled

    Abstract: No abstract text available
    Text: MITSUBISHI ALSTTLs M 74ALS1035P TËJ MITSUB ISH I {DGTL LOGIC} Q012732 G | HEX NONINVERTING BUFFER W ITH OPEN COLLECTOR OUTPUT / DESCRIPTION PIN CONFIGURATION TOP VIEW ” T h e M 7 4 A L S 1 0 3 5 P is a s e m ic o n d u c to r in te g ra te d c ir­ c u it c o n s is tin g o f six n o n -inverting b u ffe rs w ith open


    OCR Scan     		PDF 74ALS1035P Q012732 16P2P 16-PIN 150mil T-90-20 20P2V 20-PIN 300mll

    ci la 7610

    Abstract: No abstract text available
    Text: c +e MITSUBISHI ALSTTLs . op,00° M 74A L S 620A -1P v ie N v t ^s ^ - 3 _ OCTAL BUS TRANSCEIVER W ITH 3-STATE OUTPUT INVERTED 6249827 MITSUBISHI CDGTL LOGIC) DESCRIPTION The M74ALS6Í20A-1P is a semiconductor integrated cir­ cuit consisting of eight bus transm itter/receiver circuits


    OCR Scan     		PDF M74ALS6 16P2P 16-PIN 150mil T-90-20 20P2V 20-PIN 300mil ci la 7610

    ci la 7610

    Abstract: No abstract text available
    Text: MITSUBISHI ALSTTLs M 7 4 A LS 6 5 1 P 7 -52-3/ OCTAL BUS TRANSCEIVER/REGISTER W ITH 3-STATE OUTPUT INVERTED 6249827 MITSUBISHI 91 D 12674 (DGTL LOGIC ) DESCRIPTION The M74ALS651P is a semiconductor integrated circuit consisting of eight bus transceiver/registers with 3-state


    OCR Scan     		PDF M74ALS651P 16P2P 16-PIN 150mil T-90-20 20P2V 20-PIN 300mil ci la 7610

    Untitled

    Abstract: No abstract text available
    Text: MITSUBISHI íDGTL LOGICI TI DEI't.E4*1ñ27 D0ia3flD S MITSUBISHI ALSTTLs M 624 9 82 7 M IT S U B IS H I DG TL L O G IC 7 4 A 91D L S 1 1 3 A P 12380 D DUAL J-K N EG A TIVE EDGE-TRIGGERED FLIP -FLO P W IT H SET T -H (* -o 7 -o y DESCRIPTION PIN CONFIGURATION (TOP VIEW)


    OCR Scan     		PDF 74ALS113AP 16P2P 16-PIN 150mil T-90-20 20P2V 300mil

    m74als191p

    Abstract: No abstract text available
    Text: ÍDGTL LOGIC} 91D TI De | 12446 b241fl27 □ 0 1 2 4 4b ñ r D MITSUBISHI ALSTTLs M 74A LS191P SYNCHRONOUS PRESETTABLE UP/DOWN 4 -B IT BINARY COUNTER W ITH MODE CONTROL • 7 ^ V ' 5 ' ' ^ >3 DESCRIPTION - o 7 PIN CONFIGURATION TOP VIEW Th e M 7 4 A L S 1 9 1 P is a s e m ic o n d u c to r in te g ra te d c irc u it


    OCR Scan     		PDF b241fl27 LS191P 16P2P 16-PIN 150mil T-90-20 20P2V 20-PIN 300mil m74als191p

    74ALS640

    Abstract: No abstract text available
    Text: MITSUBISHI -CDGTL LOGIC} dT | ba^flS? D O i a k b B 4 M ITSUBISHI A L ST T Ls sc* -s s 5 " : . M 7 4 A LS6 4 7 P ,o.9B OCTAL BUS TR A N SC EIV ER /R EG IST ER WITH OPEN COLLECTOR OUTPUT NONINVERTED 6249827 MITSUBISHI CDGTL LOGTC) DESCRIPTION The M74ALS647P is a semiconductor integrated circuit


    OCR Scan     		PDF M74ALS647P 16P2P 16-PIN 150mil T-90-20 20P2V 20-PIN 300mil 74ALS640

    74ALS131

    Abstract: 74als245a m74als138p 74als169b 74ALS193D
    Text: M IT S U B IS H I -CDGTL L O G I C } TI 0 F | b E 4 ciflE 7 0 D lE 3 flt b |~ _ 6249827 MITSUBISHI I M IT SU B ISH I ALSTTLs M 74ALS131P <DG T L LO GI C 91D 12386 D 3 -L IN E TO 8 -L IN E D E C O D E R /D E M U L T IP L E X E R W IT H A D D R E S S R E G IS T E R


    OCR Scan     		PDF 74ALS131P M74ALS131P 16P2P 16-PIN 150mil T-90-20 20P2V 20-PIN 300mll 74ALS131 74als245a m74als138p 74als169b 74ALS193D

    Untitled

    Abstract: No abstract text available
    Text: MITSUBISHI ALSTTLs M 7 4 A L S 1 0 0 2 À P a D eE| tk24=]aS7 0015712 > | MITSUBISHI IDGTL LOGIC} 11 QUADRUPLE 2-IN P U T PO SITIVE NOR BUFFER 7 ^ V 3 - /S DESCRIPTION PIN CONFIGURATION (TOP VIEW) The M74ALS1002AP is a semiconductor integrated cir­ cuit consisting of four 2-input positive-logic NOR buffer


    OCR Scan     		PDF M74ALS1002AP 16P2P 16-PIN 150mil T-90-20 20P2V 20-PIN 300mil

    J 5027 R

    Abstract: BEM 6K
    Text: MIT SUBISH I íDGTL L O G I C } T I d ËT| ^5^027 ~JZ.SZt~3/ G0127SS □ MITSUBISHI ALSTTLs M 74A L S 1621A P I 62 49 8 2 7 M I T S U B I S H T T D G T L T o G r ^ ~ 910 12755 D OCTAL BUS TRANSCEIVER W ITH OPEN COLLECTOR OUTPUT NONINVERTED) DESCRIPTION


    OCR Scan     		PDF G0127SS M74ALS1621AP 74ALS621AP 16P2P 16-PIN 150mil T-90-20 20P2V 20-PIN 300mil J 5027 R BEM 6K

    Untitled

    Abstract: No abstract text available
    Text: MITSUBISHI ALSTTLs & M74ALS169BP T ' - v ’S '- J J - o SYNCHRONOUS PRESETTABLE UP/DOWN 4 -B IT BINARY COUNTER 6249827 MITSUBISHI DG TL LOGIC DESCRIPTION Th e M 74A L S 169 B P is a sem iconductor integrated circuit of a synchronous p resettable u p /d o w n


    OCR Scan     		PDF M74ALS169BP 16P2P 16-PIN 150mil T-90-20 20P2V 300mil

    74als561

    Abstract: No abstract text available
    Text: MITSUBISHI íDGTL LOGIC} "DÌI bSMTñE? 00123ki7 5 TI W~ M IT S U B IS H I* !L. S T T L s M74ALS38AP 91D 12367 D 6249827 MITSUBISHI DGTL LOGIC QUADRUPLE 2 -IN P U T P O S ITIV E NAND BUFFER W IT H OPEN COLLECTOR OU TPUT T - - V 3 - / S DESCRIPTION PIN CONFIGURATION (TOP VIEW)


    OCR Scan     		PDF 00123ki7 M74ALS38AP 150mil 16P2P 16-PIN T-90-20 20P2V 300mll 74als561

    Untitled

    Abstract: No abstract text available
    Text: "d ë J M ITS UBISHI -CDGTL L O G I O bEMTfla? ooiBS'in a S^Ls MITSUBISHI ALSTTLs M 74ALS133P r _ 6249827 MITSUBISHI - y j - / r SINGLE 13-IN PU T POSITIVE NAND GATE DGTL LOGIC DESCRIPTION Th e M 7 4A LS 133P is a sem iconductor integrated circuit


    OCR Scan     		PDF 74ALS133P 13-IN 13-input 16P2P 16-PIN 150mil T-90-20 20P2V 20-PIN 300mil

    m74als

    Abstract: M74ALS109AP 74ALS640
    Text: M IT S U B IS H I {D G T l T o G IcT ^ I b H 1 SS? M 6249827 MITSUBISHI 7 4 A CDGTL LOGIC 91D J STTLs L S 1 0 9 A 12 37 4 P D DUAL J-R POSITIVE EDGE-TRIGGERED FLIP-FLOP W ITH SET AND RESET T -V & -0 7 - Ô ? DESCRIPTION PIN CONFIGURATION TOP VIEW) The 74ALS109AP is a semiconductor Integrated circuit


    OCR Scan     		PDF M74ALS109AP 16P2P 16-PIN 150mil T-90-20 20P2V 20-PIN 300mil m74als 74ALS640

    gt 568

    Abstract: m74als568ap m74als568a
    Text: MITSUBISHI -CDGTL L O G I O de! TI tsMiaa? QGiasai 4 |~~ M IT S U B IS H I ALSTTLs ~ J- M 74A LS 568A P S Y N C H R O N O U S P R E S E T T A B L E U P /O O W N D EC A D E C O U N TE R _ W IT H 3 -S T A T E O U T P U T 1H249827 MITSIJBISHI


    OCR Scan     		PDF 1H249827 16P2P 150mil 20P2V 300mil E--07 gt 568 m74als568ap m74als568a

    M74ALS1032AP

    Abstract: No abstract text available
    Text: MITSUBISHI ALSTTLs M 74ALS1 0 3 2 AP M I T S U B I S H I - C D G T L L O G I C } T I D È I ” L ^ M ^ ñ S ? 1 2 7 5 fi QUADRUPLE 2-IN P U T POSITIVE OR BUFFER _ DESCRIPTION _ _ _ _ PIN CONFIGURATION TOP VIEW The M74ALS1032AP is a semiconductor integrated cir­


    OCR Scan     		PDF 74ALS1 M74ALS1032AP 16P2P 16-PIN 150mil T-90-20 20P2V 20-PIN 300mil

    Philips Semiconductors Selection Guide

    Abstract: 74ALS08
    Text: Philips Semiconductors Functional selection guide GATES FUNCTION INVERTERS NAND NOR DEVICE NUMBER NUMBER OF PINS Hex inverters 74ALS04B 14 Quad 2-input 74ALS00A 14 Triple 3-input 74ALS10A 14 Dual 4-input 74ALS20A 14 8-input 74ALS30A 14 Quint 2-input NAND, open collector


    OCR Scan     		PDF 74ALS04B 74ALS00A 74ALS10A 74ALS20A 74ALS30A 74ALS38A 74ALS02 74ALS27 74ALS08 74ALS11A Philips Semiconductors Selection Guide

    74ALS573AD

    Abstract: 74ALS574AD
    Text: M ITSUBISHI ALSTTLs r M 7 4 A L S 1 6 4 5 A P D e | bSMTfla? DDia77T 3 MITSUBISHI -CDGTL LOGIC} OCTAL BUS TR A N SC EIVER W IT H 3-STATE O U TPUT N O N IN VERTED - 7 “' » DESCRIPTION The M74ALS1645AP is a semiconductor integrated cir­ cuit consisting of eight bus transmitter/receiver circuits


    OCR Scan     		PDF DDia77T M74ALS1645AP M74ALS645AP -15mA) 150mil 16P2P 16-PIN T-90-20 20P2V 74ALS573AD 74ALS574AD

    c 2274

    Abstract: No abstract text available
    Text: '7 ' '0 7 -0 5 * MITSUBISHI ALSTTLs OCTAL D -TY P E EDGE-TRIGGERED FLIP-FLO P W IT H 3-S TA TE O U TPU T N O N IN V E R TE D . Ä > a 6249827 M IT S U B IS H I (D G TL L O G IC ) DESCRIPTION consisting o f eight D-type positive edge-triggered flipflop circuits w ith 3-state noninverted output and is pro­


    OCR Scan     		PDF M74ALS574AP 150mil 16P2P 16-PIN T-90-20 20P2V 20-PIN 300mil c 2274

    74ALS273P

    Abstract: M74ALS273P
    Text: MITSUBISHI -CDGTL LOGIC} TI D e B bSMTñE? DDIHSDI 5 MITSUBISHI ALSTTLs M 74A LS273P T z- / ù > ~ o y - < o s ' OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP FLOP WITH RESET 9 1D 12501 6249827 MITSUBISHI ÍDGTL LOgT c T DESCRIPTION PIN CONFIGURATION TOP VIEW


    OCR Scan     		PDF LS273P 74ALS273P 16P2P 16-PIN 150mil T-90-20 20P2V 20-PIN 300mil M74ALS273P