M74LS240P
Abstract: la 7610 d 667c
Text: M ITSUBISHI L S T T L s M 74LS240P OCTAL BUFFER/LINE DRIVERS WITH 3-STATE OUTPUTS INVERTED DESCRIPTION The M 74LS240P PIN CONFIGURATION (TOP VIEW) is a s e m ic o n d u c to r integrated c irc u it a n d c o m m o n o u tp u t c o n tro l in p u t f o r all 4 d iscrete c irc u its .
|
OCR Scan
|
PDF
|
M74LS240P
M74LS240P
400mV
-15mA)
16-PIN
20-PIN
la 7610
d 667c
|
M74LS640-1P
Abstract: 20P4 20-PIN
Text: MITSUBISHI LSTTLs M74LS640-1P OCTAL BUS TRANSCEIVER W ITH 3-STATE OUTPUT INVERTED DESCRIPTION PIN CONFIGURATION (TOP VIEW) The M 74L S 64 0-1P is a semiconductor integrated circuit containing 8 bus transmitters/receivers w ith inverted ou t puts. DATA
|
OCR Scan
|
PDF
|
M74LS640-
M74LS640-1P
400mV
-15mA)
16-PIN
20-PIN
20P4
|
M74LS540P
Abstract: 20-PIN
Text: MITSUBISHI LSTTLs M74LS540P OCTAL BUFFER/LINE DRIVER W ITH 3-STATE OUTPUT INVERTED DESCRIPTION The M 74L S 54 0P PIN CONFIGURATION (TOP VIEW) is a semiconductor integrated circuit _ O UTPUT containing 1 block o f buffer w ith 3-state inverted output
|
OCR Scan
|
PDF
|
M74LS540P
M74LS540P
400mV
-15mA)
16-PIN
20-PIN
|
TJ4D
Abstract: DN74LS173 MA161
Text: I DN74LS173 LS TTL DN74LS Series DN74LS173 4 -b it D-type R egisters with 3 -state Outputs P-2 • Description DN74LS173 is a 4-bit register with 3-state outputs. ■ Features • Capability for data holding irrespective o f clock pulse number • Data nondestructive during 3-state output
|
OCR Scan
|
PDF
|
DN74LS
DN74LS173
DN74LS173
16-pin
SO-16D)
TJ4D
MA161
|
AmZ8144
Abstract: AmZ8140 AmZ8140/44
Text: AmZ8140 • AmZ8144 Octal Three-State Buffers FUNCTIONAL DESCRIPTION DISTINCTIVE CHARACTERISTICS • • • • • • • • The AmZ8140 and AmZ8144 are octal buffers fabricated using advanced low -pow er Schottky technology. The 20-pin package provides improved printed circuit board density for use in m emory
|
OCR Scan
|
PDF
|
AmZ8140
AmZ8144
20-pin
IL-STD-883
AmZ8140/44
|
mitsubishi cab
Abstract: M74LS241P M74LS243P 20-PIN
Text: MITSUBISHI LSTTLs M74LS243P QUADRUPLE BUS TRANSCEIVER WITH 3-STATE OUTPUT NONINVERTED DESCRIPTION The M 74L S 24 3P PIN CONFIGURATION (TOP VIEW) is a semiconductor integrated circuit containing 4 bus transmitters/receivers w ith 3-state non inverted outputs.
|
OCR Scan
|
PDF
|
M74LS243P
M74LS243P
-15mA)
16-PIN
20-PIN
mitsubishi cab
M74LS241P
|
M74LS126AP
Abstract: 20-PIN 12kf
Text: MITSUBISHI LSTTLs M 74LS126AP Q U AD R U PLE BU S BU FFER G A TE WITH 3-STA TE O UTPUT DESCRIPTION PIN CONFIGURATION TOP VIEW The M 74LS126AP is a semiconductor integrated circuit containing 4 buffers w ith 3-state outputs and is provided w ith an o u tp u t control in p u t OC which is independent fo r
|
OCR Scan
|
PDF
|
M74LS126AP
M74LS126AP
16-PIN
20-PIN
12kf
|
Untitled
Abstract: No abstract text available
Text: AVG Semiconductors DDF Technical Data Quad 2-Input NOR Buffer with Open Collector Outputs This device contains four independent gates, each of which performs the logic NOR function. The open-collector outputs require external pull-up resistors for proper logical operation.
|
OCR Scan
|
PDF
|
DV74LS33
DV74ALS33A
AVG-001
AVG-002
ALS33A
DV74LS33,
1-800-AVG-SEMI
|
Untitled
Abstract: No abstract text available
Text: DDi AVG Semiconductors Technical Data DV74LS573 DV74ALS573B N Suffix Plastic DIP AVG-005 Case This device is an 8-bit register designed specifically for driving highly-capacitive or relatively low-impedance loads. The high impedance state and increased high-logic level
|
OCR Scan
|
PDF
|
DV74LS573
DV74ALS573B
AVG-005
AVG-006
LS573B
DV74LS573B,
0000E42
1-800-AVG-SEMI
|
Untitled
Abstract: No abstract text available
Text: GD54/74LS367A HEX BUS DRIVERS WITH 3-STATE OUTPUTS Feature • 3-State Outputs Drive Bus Line or Buffer Memory Address Registers • Choice of True or Inverting Outputs Pin Configuration Vcc G2 6A 6Y 5A 5Y 4A 4Y Description These hex buffers and line drivers are designed
|
OCR Scan
|
PDF
|
GD54/74LS367A
G054/74LS367A
667S2
|
hd74lsoop
Abstract: No abstract text available
Text: H D 74L S 126A ICIRCUIT SCHEMATIC •Quadruple Bus Buffer Gates with three-state outputs (%) IPIN ARRANGEMENT •FUNCTION TABLE Inputs C L H H Outputs Y Z H L A X H L Note) H; high level, L; low level, X; irrelevant Z; off (high-im pedance) gute of a 3 *«tate output
|
OCR Scan
|
PDF
|
HD74LS126A
T-90-10
74LSOO
ib203
hd74lsoop
|
54LS374
Abstract: CQCC1-N20 GDFP2-F20
Text: REVISIONS LTR E DESCRIPTION DATE YR-MO-DA Changed code ident. no. to 67268. Correct vendor part number. Editorial changes \throughout. Change drawing to military drawing format. Case 2 inactivated for new design. F Add device type 02. Update boilerplate.
|
OCR Scan
|
PDF
|
MIL-HDBK-103.
MIL-HDBK-103
T00470fl
54LS374
CQCC1-N20
GDFP2-F20
|
54LS28
Abstract: 54LS33 GDFP1-F14
Text: REVISIONS DATE DESCRIPTION LTR YR-MO-DA Delete CAGE 01295 from 8512601BX. Add CAGE 04713 to approved source list. Delete V qjj test; add to recommended operating conditions. Change t m g (10, 11) in table I. Table I, prop, delays, add "A or B to Y " . Prop, delays
|
OCR Scan
|
PDF
|
8512601BX.
MIL-BUL-103.
MIL-BUL-103
54LS28
54LS33
GDFP1-F14
|
N8T125N
Abstract: 1N3064 74LS 74LS245 8T125 ttl buffer 74LS245 N8T125 74LS245 SIGNETICS
Text: Signetics 8T125 Transceiver Octal 3-State Transceiver Product Specification Logic Products FEATURES • • • • • Octal bidirectional bus interface 3-State buffer outputs PNP Inputs for reduced loading Hysteresis on all Data inputs Pin compatible with 74LS245
|
OCR Scan
|
PDF
|
74LS245
8T125
8T125
500ns
1n916,
1N3064,
N8T125N
1N3064
74LS
74LS245
ttl buffer 74LS245
N8T125
74LS245 SIGNETICS
|
|
|
Untitled
Abstract: No abstract text available
Text: MITSUBISHI LSTTLs M74LS367AP H EX BUS D R IVER S W IT H 3 -S T A T E O UTPU TS DESCRIPTION The M 7 4L S 36 7A P is a semiconductor integrated circuit PIN CONFIGURATION TOP VIEW constaining 6 buffers w ith 3-state ou tp ut and is provided w ith ou tp u t control
|
OCR Scan
|
PDF
|
M74LS367AP
500ns,
b2LHfl27
0013Sbl
|
DM74LS126A
Abstract: DM74LS126AM DM74LS126AN M14A N14A
Text: DM74LS126A Quad 3-STATE Buffer transistors are turned off presenting a high-im pedance state to th e bus line. Thus the output will act neither as a sign ifi cant load nor as a driver. To m inim ize th e possibility th a t two outputs will attem pt to ta ke a com m on bus to opposite logic
|
OCR Scan
|
PDF
|
DM74LS126A
ena21
14-Lead
DM74LS126AM
DM74LS126AN
M14A
N14A
|
13005-1
Abstract: 13005 2 DM74LS645 DM74LS645N DM74LS645WM LS645
Text: S E M IC O N D U C T O R tm DM74LS645 Octal Bus Transceivers General Description Features T h e s e o c ta l b us tra n s c e iv e rs a re d e s ig n e d fo r a s y n c h ro n o u s • B i-d ire c tio n a l bu s tra n s c e iv e rs in h ig h -d e n s ity 2 0 -p in
|
OCR Scan
|
PDF
|
DM74LS645
20-pin
59B-13
20-Lead
DM74LS645WM
DM74LS645N
13005-1
13005 2
DM74LS645
LS645
|
74LS series logic gates 3 input or gate
Abstract: 54LS670 54LS670DMQB 54LS670FMQB 54LS670LMQB 74LS DM54LS670J DM54LS670W DM74LS670 DM74LS670M
Text: S E M IC O N D U C T O R tm DM74LS670 3-STATE 4-by-4 Register Files and the read tim e 24 ns typical . The register file has a non-volatile readout in that data is not lost w hen addressed. General Description These register files are organized as 4 w ords of 4 bits each,
|
OCR Scan
|
PDF
|
DM74LS670
74LS series logic gates 3 input or gate
54LS670
54LS670DMQB
54LS670FMQB
54LS670LMQB
74LS
DM54LS670J
DM54LS670W
DM74LS670
DM74LS670M
|
74LS674
Abstract: No abstract text available
Text: M MOTOROLA SN54LS/74LS673 SN54LS/74LS674 D E S C R IP T IO N — T he S N 5 4 L S /7 4 L S 6 7 3 and S N 5 4 L S /7 4 L S 6 7 4 are 3 -s ta te 1 6 -b it s h ift registers. T he L S 6 7 3 is a 1 6 -b it s h ift re g is te r and a 1 6 -b it sto ra g e re g is te r in a
|
OCR Scan
|
PDF
|
Y0-Y15
LS673
LS674
P0-P15
74LS674
|
Untitled
Abstract: No abstract text available
Text: MITSUBISHI LSTTLs M74LS643-1P OCTAL BUS TRANSC EIVER W IT H 3-S T A T E O UTPUT DESCRIPTION The M 7 4LS 643-1P is a semiconductor integrated circuit PIN CONFIGURATION TOP VIEW containing 8 bus transmitters/receivers w ith inverted and CONTRO L IN P U T non-inverted outputs.
|
OCR Scan
|
PDF
|
M74LS643-1P
643-1P
--15m
b2LHfl27
0013Sbl
14-PIN
16-PIN
20-PIN
|
74LS366AP
Abstract: No abstract text available
Text: MITSUBISHI LSTTLs M 74LS366AP H EX BUS D R IV E R W IT H 3 -S T A T E O UTPUT IN V E R T E D DESCRIPTION PIN CONFIGURATION (TOP VIEW) The M 74LS366AP is a semiconductor integrated circu it containing 6 buffers w ith 3-state outputs and is provided w ith
|
OCR Scan
|
PDF
|
74LS366AP
74LS366AP
500ns,
b2LHfl27
0013Sbl
14-PIN
16-PIN
20-PIN
|
74LS04P
Abstract: 2294a
Text: MITSUBISHI LSTTLs M74LS257AP QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER W ITH 3-STATE OUTPUT DESCRIPTION The M 7 4L S 25 7A P PIN CONFIGURATION TOP VIEW is a semiconductor integrated circuit containing fo ur 2-line to 1-line data selector/m ultiplexer
|
OCR Scan
|
PDF
|
M74LS257AP
0013Sbl
14-PIN
16-PIN
20-PIN
74LS04P
2294a
|
74LS365AP
Abstract: No abstract text available
Text: MITSUBISHI LSTTLs M 74LS 365A P HEX BUS DRIVER W ITH 3 -S T A T E OUTPUT DESCRIPTION The M 7 4L S 36 5A P is a semiconductor integrated circuit PIN CONFIGURATION TOP VIEW containing 6 buffers w ith 3-state outputs and is provided w ith o u tp ut control
|
OCR Scan
|
PDF
|
500ns,
0013Sbl
14-PIN
16-PIN
20-PIN
74LS365AP
|
Untitled
Abstract: No abstract text available
Text: MITSUBISHI LSTTLs M74LS540P OCTAL BUFFER/LINE DRIVER W ITH 3-STATE OUTPUT INVERTED DESCRIPTION The M 74L S 54 0P PIN CONFIGURATION (TOP VIEW) is a semiconductor integrated circuit _ O UTPUT containing 1 block o f buffer w ith 3-state inverted output
|
OCR Scan
|
PDF
|
M74LS540P
b2LHfl27
0013Sbl
14-PIN
16-PIN
20-PIN
|
