K6R1008V1D
Abstract: No abstract text available
Text: PRELIMINARY for AT&T CMOS SRAM K6R1008V1D Document Title 64Kx16 Bit High-Speed CMOS Static RAM 3.3V Operating Operated at Commercial and Industrial Temperature Ranges. Revision History Rev. No. History Rev. 0.0 Rev. 0.1 Rev. 0.2 Initial document. Speed bin modify
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K6R1008V1D
64Kx16
100mA
32-TSOP2-400CF
002MIN
K6R1008V1D
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CY7C4255V
Abstract: CY7C4265V CY7C4275V CY7C4285V CY7C42X5V
Text: fax id: 5422 CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V PRELIMINARY 8K/16K/32K/64Kx18 Low Voltage Deep Sync FIFOs Features Functional Description The CY7C4255/65/75/85V are high-speed, low-power, first-in first-out FIFO memories with clocked read and write interfaces. All are 18 bits wide and are pin/functionally compatible to
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CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
8K/16K/32K/64Kx18
CY7C4255/65/75/85V
CY7C42X5V
CY7C4255V
CY7C4265V
CY7C4275V
CY7C4285V
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IBM0418A11NLAA
Abstract: IBM0436A11NLAA
Text: . Preliminary IBM0436A11NLAA IBM0418A11NLAA 32Kx36 & 64Kx18 SRAM Features • 32Kx36 or 64Kx18 organizations • Registered Outputs • 0.25 Micron CMOS technology • 30 Ohm Drivers • Synchronous Pipeline Mode of Operation with Self-Timed Late Write • Common I/O
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IBM0436A11NLAA
IBM0418A11NLAA
32Kx36
64Kx18
32Kx36
nrrL3325
IBM0418A11NLAA
IBM0436A11NLAA
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MR0A16A
Abstract: 64Kx16 SRAM 64Kx16 MR0A16ACYS35 MR0A16AVYS35 MR0A16AYS35
Text: MR0A16A 64Kx16 MRAM Memory Features • Fast 35 ns Read/Write Cycle • SRAM Compatible Timing and Pin-out Uses Existing SRAM Controllers Without Redesign • Unlimited Read & Write Endurance • Data Always Non-volatile for >20-years at Temperature • One Memory Replaces Flash, SRAM, EEPROM and BBRAM in System
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MR0A16A
64Kx16
20-years
44-TSOP
48-BGA
MR0A16A
SRAM 64Kx16
MR0A16ACYS35
MR0A16AVYS35
MR0A16AYS35
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Untitled
Abstract: No abstract text available
Text: In-Circuit Programming of the MX26C1024A 1M-Bit 64Kx16 CMOS Multiple-Time-Programmable ROM Application Note 09/16/97 -This application note describes how to erase and program the MX26C1024A, 1M-bit MTP
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MX26C1024A
64Kx16)
MX26C1024A,
12-volts
500ms
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CS16LV40963
Abstract: BS62LV4006 sram cross reference CS18LV40963 LY6264 Hynix Cross Reference cs18lv10245 cs18lv02560 LY621024 K6X1008C2D
Text: www.ashlea.co.uk 01793 783784 Low power SRAM Cross Reference Density Configuration 64K 8Kx8 256K 32Kx8 Lyontek LY6264 LY62L64 LY62256 LY62L256 LY62256 2.7-5.5 1M 128Kx8 64Kx16 LY621024 LY62L1024 LY62L6416 Samsung K6X0808C1D K6X0808T1D K6X1008C2D K6X1008T2D
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32Kx8
LY6264
LY62L64
LY62256
LY62L256
LY62256
128Kx8
64Kx16
LY621024
LY62L1024
CS16LV40963
BS62LV4006
sram cross reference
CS18LV40963
LY6264
Hynix Cross Reference
cs18lv10245
cs18lv02560
LY621024
K6X1008C2D
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K6R1016C10
Abstract: k6r1016c1c
Text: K6R1016C1C-C/C-L, K6R1016C1C-I/C-P CMOS SRAM Document Title 64Kx16 Bit High-Speed CMOS Static RAM 5.0V Operating . Operated at Commercial and Industrial Temperature Ranges. Revision History Rev. No. History Draft Data Remark Rev. 0.0 Initial release with preliminary.
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K6R1016C1C-C/C-L,
K6R1016C1C-I/C-P
64Kx16
48-fine
K6R1016C1C-Z
K6R1016C1C-F
80/Typ.
25/Typ.
K6R1016C10
k6r1016c1c
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Untitled
Abstract: No abstract text available
Text: K6R1016V1C-C/C-L, K6R1016V1C-I/C-P for AT&T CMOS SRAM Document Title 64Kx16 Bit High-Speed CMOS Static RAM 3.3V Operating Operated at Commercial and Industrial Temperature Ranges. Revision History Rev. No. History Draft Data Remark Rev. 0.0 Initial release with Preliminary.
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K6R1016V1C-C/C-L,
K6R1016V1C-I/C-P
64Kx16
48-fine
K6R1016V1C-Z
K6R1016V1C-F
I/O16
002MIN
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CY7C4275V
Abstract: CY7C4285V CY7C42X5V
Text: fax id: 5422 CY7C4275V CY7C4285V PRELIMINARY 32K/64Kx18 Low Voltage Deep Sync FIFOs Features Functional Description The CY7C4275V/85V are high-speed, low-power, first-in first-out FIFO memories with clocked read and write interfaces. All are 18 bits wide and are pin/functionally compatible to
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CY7C4275V
CY7C4285V
32K/64Kx18
CY7C4275V/85V
CY7C42X5V
CY7C4275V
CY7C4285V
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29F100T
Abstract: 1 MEGA OHM RESISTOR MX29F100T 29f100
Text: MX29F100T/B 1M-BIT [128Kx8/64Kx16] CMOS FLASH MEMORY FEATURES • • • • • • • • • 5V±10% for read, erase and write operation 131072x8/ 65536x16 switchable Fast access time:55/70/90/120ns Low power consumption - 40mA maximum active current 5MHz
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MX29F100T/B
128Kx8/64Kx16]
131072x8/
65536x16
55/70/90/120ns
16K-Bytex1,
32K-Bytex1,
64K-Byte
DEC/21/1999
JUN/14/2001
29F100T
1 MEGA OHM RESISTOR
MX29F100T
29f100
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km6161000bl7
Abstract: No abstract text available
Text: Preliminary KM6161OOOBL / L-L CMOS SRAM 64Kx16 Bit CMOS Static RAM FEATURES GENERAL DESCRIPTION • Fast Access Time : 55,70 ns max. • Low Power Dissipation Standby(CMOS) :550^W (max.)L-Version : 110|iW (max.)LL-Version Operating : 660mW (max.) • Single 5V±10% Power Supply
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KM6161OOOBL
64Kx16
550MW
660mW
I/01-I/08
KM6161000BLT/LT-L:
400mil
KM6161000BLR/LR-L:
KM6161000BL/L-L
km6161000bl7
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G530T
Abstract: No abstract text available
Text: •HYUNDAI H Y 6 7 1 6 1 1 0 / 1 Ì 1 64K X 16 Bit SYNCHRONOUS CMOS SRAM PRELIMINARY DESCRIPTION This device integrates high-speed 64Kx16 SRAM core, address registers, data input registers, a 2-bit burst address counter and Non-pipelined output. All synchronous inputs pass through registers controlled by a
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64Kx16
486/Pentium
15ns/20ns/25ns
67MHz
Mb75Qflfl
GG0b313
10H07-11-MAY95
HY6716110/111
4b750flfl
1DH07-11-MAY95
G530T
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CY7C4255V
Abstract: CY7C4265V CY7C4275V CY7C4285V CY7C42X5V CY7C42X5V-ASC QO-17
Text: CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V V CYPRESS 32K/64Kx18 Low Voltage Deep Sync FIFOs Features Functional Description The CY7C4255/65/75/85V are high-speed, low-power, first-in first-out FIFO memories with clocked read and write interfac es. All are 18 bits wide and are pin/functionally compatible to
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CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
32K/64Kx
CY7C4255V)
CY7C4265V)
CY7C4275V)
CY7C4285V)
100-MHz
10-ns
CY7C4255V
CY7C4265V
CY7C4275V
CY7C4285V
CY7C42X5V
CY7C42X5V-ASC
QO-17
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metal case REGULATOR IC 7812 pin diagram
Abstract: CY7C4275 CY7C4285 CY7C42X5
Text: fax id: 5416 ^;aaazgg st CY7C4275 CY7C4285 PRELIMINARY ; U I F lm c b ti 32K/64Kx18 1 Meg Deep Sync FIFOs Functional Description Features H ig h-speed , low -pow er, first-in first-o u t F IF O m em o ries 32K x 18 (C Y 7 C 42 75 ) 64K x 18 (C Y 7 C 42 85 )
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CY7C4275
CY7C4285
32K/64Kx18
CY7C4275)
CY7C4285)
100-MHz
metal case REGULATOR IC 7812 pin diagram
CY7C4285
CY7C42X5
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Untitled
Abstract: No abstract text available
Text: ^ED I EDI8M1665C Electronic D«*igrtt Inc. High Speed Megabit SRAM Module 64Kx16 CMOS, High Speed Programmable, Static RAM Module Features The EDI8M1665C is a 1024K-bit high speed CMOS Static RAM Module consisting of four 4 64Kx4 Static RAMs in leadless chip carriers surface-mounted onto a
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EDI8M1665C
64Kx16
EDI8M1665C
1024K-bit
64Kx4
64Kx4)
64Kx16
28Kx8
256Kx4
I8M1665C
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Untitled
Abstract: No abstract text available
Text: %EDl EDI8M1664C50/60/70/85/100 Megabit SRAM Module, JEDEC Pinout 64Kx16 Static RAM CMOS, Module Features The EDI8M1664C is a high speed 64Kx16 CMOS Static RAM Module consisting of four 4 32Kx8 CMOS Static RAMs in leadless chip carriers, surface mounted onto a
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EDI8M1664C50/60/70/85/100
64Kx16
EDI8M1664C
32Kx8
32Kx16bitseach.
DQ8-DQ15)
EDI8M81664C
EDI8U1664C50/60/70/85/100
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Untitled
Abstract: No abstract text available
Text: fax id: 5416 CY7C4275 CY7C4285 32K/64Kx18 Deep Sync II FIFOs Featu res High-speed, low-power, first-in first-out FIFO memories 32K x 18 (CY7C4275) 64K x 18 (CY7C4285) 0.5 micron CMOS for optimum speed/power High-speed 100-MHz operation (10 ns read/write cycle
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CY7C4275
CY7C4285
32K/64Kx18
CY7C4275)
CY7C4285)
100-MHz
68-pin
64-pin
CY7C4275/85are
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Untitled
Abstract: No abstract text available
Text: / T T S G S 'T H O M S O N ^ 7 # GfflDIIMilLIOTMOISi M 27V102 LOW VOLTAGE 1 Megabit 64Kx16 UV EPROM and OTP EPROM • LOW VOLTAGE READ OPERATION: 3V to 5.5V > FAST ACCESS TIME: 90ns ■ LOW POWER ’’CMOS” CONSUMPTION: - Active Current 35mA - Standby Current 100|jA
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27V102
64Kx16)
FDIP40W
PLCC44
M27V102
M27C1024
M27V102
TSQP40
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Untitled
Abstract: No abstract text available
Text: Issue 2.0: July 1069 MS1664BCX-25/35 64K MS1664BCX X 16 BiCMOS SRAM Module PRELIMINARY INFORMATION 1,048,576 High Speed BiCMOS Static RAM Module. Features Pin Definition Very Fast Access Times of 25/35 nS User Configuration at, 64Kx16,128Kx8 or 256Kx4 Industry Standard 40 Pin Ceramic DIP footprint
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MS1664BCX-25/35
MS1664BCX
64Kx16
128Kx8
256Kx4
16bit
2880mW
2020mW
1590mW
MS16644BCXMB-25
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Untitled
Abstract: No abstract text available
Text: Preliminary CMOS SRAM KM6161OOOBL / L-L 64Kx16 Bit CMOS Static RAM FEATURES GENERAL DESCRIPTION • Fast Access Time : 55,70 ns max. • Low Power Dissipation Standby(CMOS) :550nW(max.)L-Version :110|iW(max.)LL-Version Operating : 660mW (max.) • Single 5V±10% Power Supply
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KM6161OOOBL
64Kx16
550nW
660mW
KM6161OOOBLT/LT-L:
400mil
KM6161OOOBLR/LR-L:
KM6161000BL/L-L
576-bit
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Untitled
Abstract: No abstract text available
Text: PRELIMINARY KM718B86 64Kx18 Synchronous SRAM 64K X 18-Bit Synchronous Burst SRAM FEATURES GENERAL DESCRIPTION • Synchronous Operation. The KM718B86 is a 1,179,648 bit Synchronous Static • On-Chip Address Counter. Random Access Memory designed to support 66MHz of
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KM718B86
64Kx18
18-Bit
KM718B86
66MHz
ofKM718B86
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Untitled
Abstract: No abstract text available
Text: 64Kx18 Synchronous SRAM KM718B86 64K X 18-Bit Synchronous Burst SRAM FEATURES GENERAL DESCRIPTION • Synchronous Operation. • On-Chip Address Counter. The KM718B86 is a 1,179,648 bit Synchronous Static Random Access Memory designed to support 66MHz of Intel secondary caches. It is organized as 65,536 words
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64Kx18
KM718B86
18-Bit
KM718B86
66MHz
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Untitled
Abstract: No abstract text available
Text: Preliminary CMOS SRAM KM616V1002B/BL, KM616V1002BI/BLI Document Title 64Kx16 Bit High Speed Static RAM 3.3V Operating , Revolutionary Pin out. Operated at Commercial and Industrial Temperature Range. Revision History Rev No. History Draft Data Remark Rev. 0.0
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KM616V1002B/BL,
KM616V1002BI/BLI
64Kx16
June-1997
44-SOJ-400
44-TSOP2-400F
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Untitled
Abstract: No abstract text available
Text: “H Y U N D A I H Y 6 7 1 6 1 0 0 /1 0 1 64K x 16 Bit SYNCHRONOUS CMOS SRAM P RELIM IN ARY DESCRIPTION This device integrates high-speed 64Kx16 SR A M core, address registers, data input registers, a 2-bit burst address counter and pipelined output. All synchronous inputs pass through registers controlled by a positive-edge
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64Kx16
486/Pentium
6ns/9ns/12ns
75MHz
486/Pe
10H05-11-MAY95
HY6716100/101
1DH05-11-MAY95
HY6716100C
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