THC63LVDM83A
Abstract: THC63LVD813 30 lvds LVDS 18bit THine THC63LVD823 THC63LVD823 application notes TD227 lvds 6bit thine electronic
Text: Preliminary THC63LVD813 Rev.0.62 THine THC63LVD813 Dual 170MHz Link LVDS Transmitter for SXGA/SXGA+/UXGA General Description Features The THC63LVD813 transmitter is designed to support Dual Link transmission between Host and Flat Panel Display up to UXGA resolutions.
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THC63LVD813
THC63LVD813
170MHz)
48bits
85MHz,
595Mbps
85MHz
THC63LVDM83A
30 lvds
LVDS 18bit
THine
THC63LVD823
THC63LVD823 application notes
TD227
lvds 6bit
thine electronic
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LVDS Transmitter THine
Abstract: THC63LVD823 tft lvds HSYNC, VSYNC, DE, input, output Diode B2x THC63LVDM83R 15 TFT 20 pin lvds dual pixel lvds 1 channel 6bit lvds driver thine electronic
Text: THC63LVD823_Rev2.0 THC63LVD823 Single 135MHz /Dual(170MHz) Link LVDS Transmitter for SXGA/SXGA+/UXGA General Description Features The THC63LVD823 transmitter is designed to support Single Link transmission between Host and Flat Panel Display up to SXGA+ resolutions and Dual Link transmission between Host and Flat Panel Display up to
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THC63LVD823
THC63LVD823
135MHz
170MHz)
48bits
135MHz,
945Mbps
LVDS Transmitter THine
tft lvds
HSYNC, VSYNC, DE, input, output
Diode B2x
THC63LVDM83R
15 TFT 20 pin lvds
dual pixel lvds
1 channel 6bit lvds driver
thine electronic
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DS90C387R
Abstract: No abstract text available
Text: November 2000 DS90C387R 85MHz Dual 12-Bit Double Pumped Input LDI Transmitter - VGA/UXGA General Description The DS90C387R transmitter is designed to support pixel data transmission from a Host to a Flat Panel Display up to UXGA resolution. It is designed to be compatible with Graphics Memory Controller Hub GMCH by implementing two
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DS90C387R
85MHz
12-Bit
DS90C387R
12-bit(
24-bit
48-bit
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MAX9213ETM
Abstract: No abstract text available
Text: 19-2828; Rev 1; 7/03 Programmable DC-Balanced 21-Bit Serializers Features ♦ Programmable DC-Balanced or Non-DC-Balanced Operation ♦ DC Balance Allows AC-Coupling for Ground-Shift Tolerance ♦ As Low as 8MHz Operation Two frequency ranges and two DC-balance default
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21-Bit
MAX9209/MAX9211/MAX9213/MAX9215
MAX9210/
MAX9212/MAX9214/MAX9216
T4877-1
MAX9213ETM
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Untitled
Abstract: No abstract text available
Text: 19-2864; Rev 4; 3/05 Programmable DC-Balance 21-Bit Deserializers The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/ MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a separate supply, allowing 1.8V to 5V output logic levels.
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21-Bit
MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/
MAX9222
MAX9209/MAX9211/MAX9213/
MAX9215
MAX9210/MAX9212/MAX9214/MAX9216
D222EUM
MAX9220EUM
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DS90CR216A
Abstract: DS90CR218A MAX9210 MAX9215 MAX9222
Text: 19-2864; Rev 4; 3/05 Programmable DC-Balance 21-Bit Deserializers The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/ MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a separate supply, allowing 1.8V to 5V output logic levels.
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21-Bit
MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/
MAX9222
MAX9209/MAX9211/MAX9213/
MAX9215
MAX9210/MAX9212/MAX9214/MAX9216
DS90CR216A
DS90CR218A
MAX9210
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MAX9220EUM
Abstract: No abstract text available
Text: 19-2864; Rev 1; 10/03 Programmable DC-Balance 21-Bit Deserializers The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/ MAX9222 feature programmable DC balance, which allows isolation between a serializer and deserializer using AC-coupling. A deserializer decodes data transmitted by a MAX9209/MAX9211/MAX9213/MAX9215
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21-Bit
MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/
MAX9222
MAX9209/MAX9211/MAX9213/MAX9215
MAX9210/MAX9212/MAX9214/MAX9216
DS90CR216A
DS90CR218A.
MAX9220/MAX9222
non-DC-balanMAX9220/MAX9222
MAX9220EUM
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Diode B2x
Abstract: THC63LVD824 THC63LVDF84B thine electronic
Text: THC63LVD824 _Rev2.0 THC63LVD824 Single 135MHz /Dual(170MHz) Link LVDS Receiver for XGA/SXGA/SXGA+/UXGA General Description Features The THC63LVD824 receiver is designed to support Single Link transmission between Host and Flat Panel Display up to SXGA+ resolutions and Dual Link transmission between Host and Flat Panel Display up to
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THC63LVD824
135MHz
170MHz)
THC63LVD824
48bits
135MHz,
945Mbps
Diode B2x
THC63LVDF84B
thine electronic
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FIN1216
Abstract: FIN1215 FIN1215MTDX FIN1216MTDX FIN1217 FIN1217MTDX FIN1218 FIN1218MTDX
Text: FIN1215 / FIN1216 / FIN1217/ FIN1218 LVDS 21-Bit Serializers / De-Serializers Features Description The FIN1217 and FIN1215 transform 21-bit wide parallel LVTTL Low-Voltage TTL data into three serial LVDS (Low-Voltage Differential Signaling) data
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FIN1215
FIN1216
FIN1217/
FIN1218
21-Bit
20MHz
85MHz
785Gbps
595Mbps
TIA/EIA-644
FIN1215MTDX
FIN1216MTDX
FIN1217
FIN1217MTDX
FIN1218
FIN1218MTDX
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Untitled
Abstract: No abstract text available
Text: THC63LVD1027_Rev.2.0_E THC63LVD1027 85MHz 10Bits Dual LVDS Repeater General Description Features The THC63LVD1027 LVDS Low Voltage Differential Signaling repeater is designed to support pixel data transmission between Host and Flat Panel Display up to WUXGA resolution.
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THC63LVD1027
THC63LVD1027
85MHz
10Bits
85MHz,
30bits
595Mbps
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Untitled
Abstract: No abstract text available
Text: FIN3385 / FIN3386 Low-Voltage, 28-Bit, Flat-Panel Display Link Serializer / Deserializer Features Description • • The FIN3385 and FIN3386 transform 28-bit wide parallel Low-Voltage TTL LVTTL data into four serial Low Voltage Differential Signaling (LVDS) data streams. A
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FIN3385
FIN3386
28-Bit
28-Bit,
20MHz
85MHz
38Gbps)
TIA/EIA-644
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UTP cat 6 cable
Abstract: No abstract text available
Text: 19-2828; Rev 5; 3/12 KIT ATION EVALU E L B A IL AVA Programmable DC-Balanced 21-Bit Serializers Features The MAX9209/MAX9213 serialize 21 bits of LVTTL/ LVCMOS parallel input data to three LVDS outputs. A parallel rate clock on a fourth LVDS output provides
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21-Bit
DS90CR215
DS90CR217
785Gbps
TIA/EIA-644
48-Lead
3AX9215.
UTP cat 6 cable
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FIN3385
Abstract: FIN3383 FIN3383MTD FIN3384 FIN3384MTD FIN3385MTD FIN3386 FIN3386MTD MTD56
Text: Revised April 2005 FIN3385 • FIN3383 • FIN3384 • FIN3386 Low Voltage 28-Bit Flat Panel Display Link Serializers/Deserializers General Description Features The FIN3385 and FIN3383 transform 28 bit wide parallel LVTTL Low Voltage TTL data into 4 serial LVDS (Low
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FIN3385
FIN3383
FIN3384
FIN3386
28-Bit
FIN3385
FIN3383
FIN3386
FIN3384
FIN3383MTD
FIN3384MTD
FIN3385MTD
FIN3386MTD
MTD56
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THC63LVDF84A
Abstract: THC63LVD824 THC63LVD814 thine electronic
Text: THine THC63LVD824 Rev.1.03 THC63LVD824 Single 135MHz /Dual(170MHz) Link LVDS Receiver for XGA/SXGA/SXGA+/UXGA General Description Features The THC63LVD824 receiver is designed to support Single Link transmission between Host and Flat Panel Display up to SXGA+ resolutions and Dual Link transmission between Host and Flat Panel Display up to
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THC63LVD824
THC63LVD824
135MHz
170MHz)
48bits
135MHz,
945Mbps
THC63LVDF84A
THC63LVD814
thine electronic
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288a
Abstract: DS90CR217 DS90CR218A DS90CR218AMTD MTD48 LINK12 AN-1041 AN1041
Text: ご注意：この日本語データシートは参考資料として提供しており内容が最新でない 場合があります。製品のご検討およびご採用に際しては、必ず最新の英文デー タシートをご確認ください。
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DS90CR218A3
85MHz
595Mbps
785Gbit/sec
233MB/sec)
DS90CR218A
785Gbit/s
223Mbytes/s
288a
DS90CR217
DS90CR218A
DS90CR218AMTD
MTD48
LINK12
AN-1041
AN1041
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Untitled
Abstract: No abstract text available
Text: 19-2864; Rev 5; 11/07 Programmable DC-Balance 21-Bit Deserializers The MAX9210/MAX9214/MAX9220/MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a separate supply, allowing
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21-Bit
MAX9210/MAX9214/MAX9220/MAX9222
MAX9209/MAX9213
MAX9210/MAX9214
MAX9212/MAX9216
MAX9210/MAX9214/MAX9220/MAX9222
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Untitled
Abstract: No abstract text available
Text: FIN1215 / FIN1216 / FIN1217/ FIN1218 LVDS 21-Bit Serializers / De-Serializers Features Description ̇ ̇ ̇ ̇ ̇ ̇ ̇ ̇ ̇ ̇ The FIN1217 and FIN1215 transform 21-bit wide parallel LVTTL Low-Voltage TTL data into three serial LVDS (Low-Voltage Differential Signaling) data
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FIN1215
FIN1216
FIN1217/
FIN1218
21-Bit
FIN1217
20MHz
85MHz
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Untitled
Abstract: No abstract text available
Text: THC63LVD1027_Rev.2.0_E THC63LVD1027 85MHz 10Bits Dual LVDS Repeater General Description Features The THC63LVD1027 LVDS Low Voltage Differential Signaling repeater is designed to support pixel data transmission between Host and Flat Panel Display up to WUXGA resolution.
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THC63LVD1027
THC63LVD1027
85MHz
10Bits
85MHz,
30bits
595Mbps
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FIN3385MTDX
Abstract: FIN3386MTDX 3385 FIN3383 FIN3383MTDX FIN3384 FIN3384MTDX FIN3385 FIN3386
Text: FIN3385 / FIN3383 / FIN3384 / FIN3386 Low-Voltage 28-Bit Flat Panel Display Link Serializer / Deserializer Features Description The FIN3385 and FIN3383 transform 28-bit wide parallel LVTTL Low-Voltage TTL data into four serial LVDS (Low Voltage Differential Signaling) data streams.
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FIN3385
FIN3383
FIN3384
FIN3386
28-Bit
20MHz
85MHz
38Gbps)
TIA/EIA-644
56-Lead
FIN3385MTDX
FIN3386MTDX
3385
FIN3383MTDX
FIN3384MTDX
FIN3386
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Untitled
Abstract: No abstract text available
Text: DS90C387R www.ti.com SNLS062E – MAY 2004 – REVISED MAY 2004 DS90C387R 85MHz Dual 12-Bit Double Pumped Input LDI Transmitter - VGA/UXGA Check for Samples: DS90C387R FEATURES DESCRIPTION • The DS90C387R transmitter is designed to support pixel data transmission from a Host to a Flat Panel
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DS90C387R
SNLS062E
DS90C387R
85MHz
12-Bit
76Gbps
24-bit
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DS90CR215
Abstract: DS90CR217 MAX9209 MAX9209ETM MAX9209EUM MAX9209GUM MAX9213 marking code 56l MAX9213ETM
Text: 19-2828; Rev 4; 10/07 Programmable DC-Balanced 21-Bit Serializers Features The MAX9209/MAX9213 serialize 21 bits of LVTTL/ LVCMOS parallel input data to three LVDS outputs. A parallel rate clock on a fourth LVDS output provides timing for deserialization.
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21-Bit
MAX9209/MAX9213
MAX9210/MAX9214
21-bit
DS90CR215
DS90CR217.
MAX9211
MAX9215.
DS90CR217
MAX9209
MAX9209ETM
MAX9209EUM
MAX9209GUM
MAX9213
marking code 56l
MAX9213ETM
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MTD48
Abstract: transmission line theory 288a DS90CR217 DS90CR218A DS90CR218AMTD an-806 Link12 AN1108
Text: ご注意：この日本語データシートは参考資料として提供しており内容が最新でない 場合があります。製品のご検討およびご採用に際しては、必ず最新の英文デー タシートをご確認ください。
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DS90CR218A3
85MHz
595Mbps
785Gbit/sec
233MB/sec)
DS90CR218A
785Gbit/s
223Mbytes/s
MTD48
transmission line theory
288a
DS90CR217
DS90CR218A
DS90CR218AMTD
an-806
Link12
AN1108
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THC63LVD824A
Abstract: 824A 16 PIN TTL parallel to vga THC63LVD824 THC63LVDF84B
Text: THC63LVD824A _Rev1.10_E THC63LVD824A Single 112MHz /Dual(170MHz) Link LVDS Receiver for XGA/SXGA/SXGA+/UXGA General Description Features The THC63LVD824A receiver is designed to support Single Link transmission between Host and Flat Panel Display up to SXGA resolutions and Dual Link transmission between Host and Flat Panel Display up to
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THC63LVD824A
112MHz
170MHz)
THC63LVD824A
48bits
112MHz,
784Mbps
824A 16 PIN
TTL parallel to vga
THC63LVD824
THC63LVDF84B
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THC63LVD824A
Abstract: THC63LVD824 THC63LVDF84B HSYNC, VSYNC, DE, input, output
Text: THC63LVD824A _Rev1.00_E THC63LVD824A Single 112MHz /Dual(170MHz) Link LVDS Receiver for XGA/SXGA/SXGA+/UXGA General Description Features The THC63LVD824A receiver is designed to support Single Link transmission between Host and Flat Panel Display up to SXGA resolutions and Dual Link transmission between Host and Flat Panel Display up to
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THC63LVD824A
112MHz
170MHz)
THC63LVD824A
48bits
112MHz,
784Mbps
THC63LVD824
THC63LVDF84B
HSYNC, VSYNC, DE, input, output
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