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    112MHZ Search Results

    112MHZ Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    DS90CR483VJDX/NOPB Texas Instruments 48-Bit Channel Link Serializer - 33-112MHz 100-TQFP -10 to 70 Visit Texas Instruments
    DS90CR483VJD/NOPB Texas Instruments 48-Bit Channel Link Serializer - 33-112MHz 100-TQFP -10 to 70 Visit Texas Instruments
    DS90CR484VJD/NOPB Texas Instruments 48-Bit Channel Link Deserializer - 33-112MHz 100-TQFP Visit Texas Instruments
    TFP201APZP Texas Instruments PanelBus DVI Receiver 112MHz, HSYNC fix 100-HTQFP 0 to 70 Visit Texas Instruments
    TFP201APZPG4 Texas Instruments PanelBus DVI Receiver 112MHz, HSYNC fix 100-HTQFP 0 to 70 Visit Texas Instruments
    SF Impression Pixel

    112MHZ Price and Stock

    Renesas Electronics Corporation FXTC-HE73TC-4.112 MHZ

    XTAL OSC TCXO 4.1120MHZ HCMOS
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    DigiKey FXTC-HE73TC-4.112 MHZ
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    CTS Corporation VFT5V-3B-901.12MHZ

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    Bristol Electronics VFT5V-3B-901.12MHZ 50 1
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    . VFT5V-3B-901.12MHZTR

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    Bristol Electronics VFT5V-3B-901.12MHZTR 3 1
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    Bourns Inc SRR3011-2R5YL

    Power Inductors - SMD 2.5uH 15% SMD 3011
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    TTI SRR3011-2R5YL Reel 58,800 1,200
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    SRR3011-2R5YL Cut Tape 25
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    Bourns Inc SRN5040TA-1R5M

    Power Inductors - SMD 1.5uH 4.5A
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    TTI SRN5040TA-1R5M Reel 1,500
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    112MHZ Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: THC63LVD104S _Rev.2.1_E THC63LVD104S 112MHz 30Bits Color LVDS Receiver General Description Features The THC63LVD104S receiver is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to SXGA resolutions. The THC63LVD104S converts the LVDS data streams back


    Original     		PDF THC63LVD104S 112MHz 30Bits THC63LVD104S 35bits 112MHz, 784Mbps

    THC63LVD104c

    Abstract: THC63LVD104A THC63LVD104 Thine 784-Mbps THC63LVDF64x lvds to NTSC
    Text: THC63LVD104C_Rev.1.10_E THC63LVD104C 112MHz 30Bits COLOR LVDS Receiver General Description Features The THC63LVD104C receiver is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to SXGA resolutions. The THC63LVD104C converts the LVDS data streams back


    Original     		PDF THC63LVD104C THC63LVD104C 112MHz 30Bits 35bits 112MHz, 784Mbps THC63LVD104A THC63LVD104 Thine 784-Mbps THC63LVDF64x lvds to NTSC

    SiI151B

    Abstract: SiI151BCT100 SII151 HSYNC, VSYNC, DE, input, output 151b MS-026-AED
    Text: SiI151B PanelLink Receiver Datasheet September 2001 General Description Features The SiI151B receiver uses PanelLink Digital technology to support high resolution displays up to SXGA 25Mhz-112Mhz . The SiI151B receiver supports up to true color panels (24 bit/pixel, 16.7M colors) in 1 or 2


    Original     		PDF SiI151B 25Mhz-112Mhz) SiI151BCT100 SiI-DS-0051-A 1-888-PanelLink SII151 HSYNC, VSYNC, DE, input, output 151b MS-026-AED

    Untitled

    Abstract: No abstract text available
    Text: LVDS Interface ICs 27bit LVDS Transmitter BU90T81 ●General Description The BU90T81 transmitter operates from 20MHz to 112MHz wide clock range, and 27bits data of parallel LVCMOS level inputs R/G/B24bits and VSYNC,HSYNC,DE are converted to four channels of LVDS data stream. Data is


    Original     		PDF 27bit BU90T81 BU90T81 20MHz 112MHz 27bits R/G/B24bits 24bits

    THC63LVD824A

    Abstract: 824A 16 PIN TTL parallel to vga THC63LVD824 THC63LVDF84B
    Text: THC63LVD824A _Rev1.10_E THC63LVD824A Single 112MHz /Dual(170MHz) Link LVDS Receiver for XGA/SXGA/SXGA+/UXGA General Description Features The THC63LVD824A receiver is designed to support Single Link transmission between Host and Flat Panel Display up to SXGA resolutions and Dual Link transmission between Host and Flat Panel Display up to


    Original     		PDF THC63LVD824A 112MHz 170MHz) THC63LVD824A 48bits 112MHz, 784Mbps 824A 16 PIN TTL parallel to vga THC63LVD824 THC63LVDF84B

    THC63LVD824A

    Abstract: THC63LVD824 THC63LVDF84B HSYNC, VSYNC, DE, input, output
    Text: THC63LVD824A _Rev1.00_E THC63LVD824A Single 112MHz /Dual(170MHz) Link LVDS Receiver for XGA/SXGA/SXGA+/UXGA General Description Features The THC63LVD824A receiver is designed to support Single Link transmission between Host and Flat Panel Display up to SXGA resolutions and Dual Link transmission between Host and Flat Panel Display up to


    Original     		PDF THC63LVD824A 112MHz 170MHz) THC63LVD824A 48bits 112MHz, 784Mbps THC63LVD824 THC63LVDF84B HSYNC, VSYNC, DE, input, output

    Untitled

    Abstract: No abstract text available
    Text: LVDS Interface ICs 27bit LVDS Transmitter BU90T81 ●General Description The BU90T81 transmitter operates from 20MHz to 112MHz wide clock range, and 27bits data of parallel LVCMOS level inputs R/G/B24bits and VSYNC,HSYNC,DE are converted to four channels of LVDS data stream. Data is


    Original     		PDF 27bit BU90T81 BU90T81 20MHz 112MHz 27bits R/G/B24bits 24bits

    THC63LVD104A

    Abstract: THC63LVD104S THC63LVD104 thine electronic
    Text: THC63LVD104S Rev.1.0 THC63LVD104S 112MHz 30Bits Color LVDS Receiver General Description Features The THC63LVD104S receiver is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to SXGA resolutions. The THC63LVD104S converts the LVDS data streams back


    Original     		PDF THC63LVD104S THC63LVD104S 112MHz 30Bits 35bits 112MHz, 784Mbps THC63LVD104A THC63LVD104 thine electronic

    BU90T81

    Abstract: No abstract text available
    Text: BU90T81 LVDS Interface ICs 27bit LVDS Transmitter BU90T81 ●General Description The BU90T81 transmitter operates from 20MHz to 112MHz wide clock range, and 27bits data of parallel LVCMOS level inputs R/G/B24bits and VSYNC,HSYNC,DE are converted to four channels of LVDS data stream. Data is


    Original     		PDF BU90T81 27bit BU90T81 20MHz 112MHz 27bits R/G/B24bits

    Untitled

    Abstract: No abstract text available
    Text: Datasheet LVDS Interface LSI 35bit LVDS Receiver 5:35 DeSerializer BU90R104 ●General Description The BU90R104 receiver operates from 8MHz to 112MHz wide clock range. The BU90R104 converts the LVDS serial data streams back into 35bits of LVCMOS parallel data.


    Original     		PDF 35bit BU90R104 BU90R104 112MHz 35bits TQFP64V

    Untitled

    Abstract: No abstract text available
    Text: THC63LVD104C_Rev.2.1_E THC63LVD104C 112MHz 30Bits COLOR LVDS Receiver General Description Features The THC63LVD104C receiver is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to SXGA resolutions. The THC63LVD104C converts the LVDS data streams back


    Original     		PDF THC63LVD104C THC63LVD104C 112MHz 30Bits 35bits 112MHz, 784Mbps

    THC63LVD104s

    Abstract: THC63LVD104A 784m THC63LVD104
    Text: THC63LVD104S _Rev.1.20_E THC63LVD104S 112MHz 30Bits Color LVDS Receiver General Description Features The THC63LVD104S receiver is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to SXGA resolutions. The THC63LVD104S converts the LVDS data streams back


    Original     		PDF THC63LVD104S 112MHz 30Bits THC63LVD104S 35bits 112MHz, 784Mbps THC63LVD104A 784m THC63LVD104

    THC63LVD104C

    Abstract: thc63lvd104c_rev.1.00_e THC63LVD104A lvds cable lvds to NTSC THC63LV Thine lvds receiver
    Text: THC63LVD104C_Rev.1.00_E THC63LVD104C 112MHz 30Bits COLOR LVDS Receiver General Description Features The THC63LVD104C receiver is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to SXGA resolutions. The THC63LVD104C converts the LVDS data streams back


    Original     		PDF THC63LVD104C THC63LVD104C 112MHz 30Bits 35bits 112MHz, 784Mbps thc63lvd104c_rev.1.00_e THC63LVD104A lvds cable lvds to NTSC THC63LV Thine lvds receiver

    Untitled

    Abstract: No abstract text available
    Text: DS90CR486 www.ti.com SNLS149C – FEBRUARY 2003 – REVISED MARCH 2013 DS90CR486 133MHz 48-Bit Channel Link Deserializer 6.384 Gbps Check for Samples: DS90CR486 FEATURES 1 • • • • • • 2 • • • • • Up to 6.384 Gbps Throughput 66MHz to 133MHz Input Clock Support


    Original     		PDF DS90CR486 SNLS149C DS90CR486 133MHz 48-Bit 66MHz 133MHz 100-pin

    SLOS602A

    Abstract: TLV320AIC3204 TLV320AIC3204IRHBR AIC3204 TLV320AIC3204IRHBT TPA2012 SLOS602 583d
    Text: TLV320AIC3204 Ultra Low Power Stereo Audio Codec www.ti.com SLOS602A – SEPTEMBER 2008 – REVISED OCTOBER 2008 1 Introduction • • 1.1 Features • • • • • • • • • • • • • • Stereo Audio DAC with 100dB SNR 4.1mW Stereo 48ksps DAC Playback


    Original     		PDF TLV320AIC3204 SLOS602A 100dB 48ksps 32-pin SLOS602A TLV320AIC3204 TLV320AIC3204IRHBR AIC3204 TLV320AIC3204IRHBT TPA2012 SLOS602 583d

    JEDEC Package Code MS-026-AED

    Abstract: SiI150ACT100 Remote Control tx2 8 pin SiI-AN-0007 JEDEC MS-026 footprint 32 pin SiI-AN-0007-A
    Text: SiI 150A PanelLink Digital Transmitter July 2000 General Description Features As the universal transmitter, SiI 150A uses PanelLink Digital technology to support displays ranging from VGA to SXGA 25-112 MHz . The SiI 150A transmitter supports up to true color panels (24 bit/pixel, 16.7M colors) in 1 or


    Original     		PDF SiI/DS-0006-C JEDEC Package Code MS-026-AED SiI150ACT100 Remote Control tx2 8 pin SiI-AN-0007 JEDEC MS-026 footprint 32 pin SiI-AN-0007-A

    transistor d 1933

    Abstract: MSK1933-0 MSK1933-2 MSK1933-4 RS170
    Text: ISO-9001 CERTIFIED BY DSCC M.S.KENNEDY CORP. ULTRA HIGH SPEED/VOLTAGE NEGATIVE OUTPUT VIDEO AMPLIFIER 1933 SERIES 4707 Dey Road Liverpool, N.Y. 13088 315 701-6751 MIL-PRF-38534 CERTIFIED FEATURES: Low Cost Complete Amplifier System 100Vpp Output Signal Into 10pF


    Original     		PDF ISO-9001 MIL-PRF-38534 100Vpp 50Vpp 1933U-4 1933S-6 1933D-6 1933U-6 -120V transistor d 1933 MSK1933-0 MSK1933-2 MSK1933-4 RS170

    SiI154CT64

    Abstract: SiI154 SiI-AN-0022 SILICON IMAGE APPLICATION NOTES
    Text: SiI 154 Preliminary Data Sheet General Description Features The SiI154 transmitter uses PanelLink Digital technology to support displays ranging from VGA to SXGA resolutions 25-112MPps in a single link interface. The SiI154 transmitter has a highly flexible


    Original     		PDF SiI154 25-112MPps) 12-bit 24-bit 24-bit 12-bit SiI154CT64 SiI/DS-0010-D 1-888-PanelLink SiI-AN-0022 SILICON IMAGE APPLICATION NOTES

    AN-1059

    Abstract: AN-1163 DS90C387 DS90CF384A DS90CF386 DS90CF388
    Text: DS90C387/DS90CF388 Dual Pixel LVDS Display Interface LDI -SVGA/QXGA General Description Features The DS90C387/DS90CF388 transmitter/receiver pair is designed to support dual pixel data transmission between Host and Flat Panel Display up to QXGA resolutions. The transmitter converts 48 bits (Dual Pixel 24-bit color) of CMOS/TTL


    Original     		PDF DS90C387/DS90CF388 DS90C387/DS90CF388 24-bit 112MHz, 672Mbps, 38Gbps AN-1059 AN-1163 DS90C387 DS90CF384A DS90CF386 DS90CF388

    log tx2 1122

    Abstract: LG.Philips LCD circuit DFP 830 MDR connector 20pin LG.Philips LCD LM220W1-A2MN lcd Inverter Delta MDR dfp 26 pin plug dfp cable D8211
    Text: SPECIFICATIONS TITLE: LM220W1-A2MN LIQUID CRYSTAL DISPLAY LM220W1 REV. 1.0 PAGE 1 OF 1 DATA DISPLAY AG LM220W1-A2MN 22“ TFT LCD PRELIMINARY SPECIFICATION The information given in this document is carefully checked and believed to be reliable. Data Display reserves the right to


    Original     		PDF LM220W1-A2MN LM220W1 LM220W1-A2MN D-82110 SiI150 log tx2 1122 LG.Philips LCD circuit DFP 830 MDR connector 20pin LG.Philips LCD lcd Inverter Delta MDR dfp 26 pin plug dfp cable D8211

    Untitled

    Abstract: No abstract text available
    Text: DS90CR483A, DS90CR484A www.ti.com SNLS291A – APRIL 2008 – REVISED APRIL 2013 DS90CR483A / DS90CR484A 48-Bit LVDS Channel Link SER/DES – 33 - 112 MHz Check for Samples: DS90CR483A, DS90CR484A FEATURES 1 • • • 2 • • • • • • • • •


    Original     		PDF DS90CR483A, DS90CR484A SNLS291A DS90CR483A DS90CR484A 48-Bit

    Untitled

    Abstract: No abstract text available
    Text: DS90CR481, DS90CR482 www.ti.com SNLS137D – NOVEMBER 2000 – REVISED APRIL 2013 DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz Check for Samples: DS90CR481, DS90CR482 FEATURES 1 • • • • 2 • • • • • • • • 3.168 Gbits/sec Bandwidth with 66 MHz Clock


    Original     		PDF DS90CR481, DS90CR482 SNLS137D DS90CR481 DS90CR482 48-Bit

    Untitled

    Abstract: No abstract text available
    Text: FemtoClock Multi-Rate 3.3V LVPECL Frequency Synthesizer ICS843034I-06 DATA SHEET GENERAL DESCRIPTION FEATURES The ICS843034I-06 is a general purpose, low phase ICS noise LVPECL synthesizer which can generate HiPerClockS™ frequencies for a wide variety of applications. The


    Original     		PDF ICS843034I-06 ICS843034I-06

    Untitled

    Abstract: No abstract text available
    Text: TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP www.ti.com SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 1 Introduction 1.1 Features 1.2 • • • • • • • • • • • • • • • • • • • • • • •


    Original     		PDF TLV320AIC3254 SLAS549A 100dB 48ksps 32-pin