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    38K15 Search Results

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    38K15 Price and Stock

    JW Winco Inc 2243-38-K15-5/8-AL-KU

    15mm x5/8"OldhamCouplng w/Keyway
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey 2243-38-K15-5/8-AL-KU Box 5 1
    • 1 $65.71
    • 10 $65.71
    • 100 $65.71
    • 1000 $65.71
    • 10000 $65.71
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    JW Winco Inc 2243-38-K15-3/4-AL-KU

    15mm x3/4"OldhamCouplng w/Keyway
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey 2243-38-K15-3/4-AL-KU Box 5 1
    • 1 $65.71
    • 10 $65.71
    • 100 $65.71
    • 1000 $65.71
    • 10000 $65.71
    		Buy Now

    JW Winco Inc 2242-38-K15-3/4-AL-KU

    15mm x3/4"OldhamCouplng w/Keyway
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey 2242-38-K15-3/4-AL-KU Box 5 1
    • 1 $82.88
    • 10 $82.88
    • 100 $82.88
    • 1000 $82.88
    • 10000 $82.88
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    JW Winco Inc 2242-38-K15-1/2-AL-KU

    15mm x1/2"OldhamCouplng w/Keyway
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey 2242-38-K15-1/2-AL-KU Box 5 1
    • 1 $82.88
    • 10 $82.88
    • 100 $82.88
    • 1000 $82.88
    • 10000 $82.88
    		Buy Now

    JW Winco Inc 2243-38-K15-1/2-AL-KU

    15mm x1/2"OldhamCouplng w/Keyway
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey 2243-38-K15-1/2-AL-KU Box 5 1
    • 1 $65.71
    • 10 $65.71
    • 100 $65.71
    • 1000 $65.71
    • 10000 $65.71
    		Buy Now
    Find more 38K15 price and stock on Findchips.com

    38K15 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    38K30

    Abstract: DELTA39K
    Text: USE DELTA39K FOR Quantum38K™ ISR™ ALL NEW DESIGNS CPLD Family CPLDs Designed for Migration Features • High density — 30K to 100K usable gates — 512 to 1536 macrocells — 136 to 302 maximum I/O pins — Eight dedicated inputs including four clock pins and


    Original     		PDF DELTA39KTM Quantum38KTM 16-Kb 48-Kb 125-MHz 18-mm Quantum38K30 Quantum38K50 Quantum38K Delta39K 38K30

    100K preset horizontal

    Abstract: LB 124 d LB 124 transistor verilog code for implementation of eeprom 38K30 j510
    Text: Quantum38K ISR™ CPLD Family PRELIMINARY CPLDs Designed for Migration Features • High density — 30K to 100K usable gates — 512 to 1536 macrocells — 136 to 302 maximum I/O pins — Eight Dedicated Inputs including four clock pins and four global I/O control signal pins; four JTAG interface pins for reconfigurability/boundary scan


    Original     		PDF Quantum38KTM CY38K100 208-pin 208EQFP) Quantum38K30 Quantum38K50 Quantum38K 100K preset horizontal LB 124 d LB 124 transistor verilog code for implementation of eeprom 38K30 j510

    Untitled

    Abstract: No abstract text available
    Text: Quantum38K ISR™ CPLD Family CPLDs Designed for Migration Features • High density — 30K to 100K usable gates — 512 to 1536 macrocells — 136 to 302 maximum I/O pins — Eight dedicated inputs including four clock pins and four global I/O control signal pins; four JTAG


    Original     		PDF Quantum38Kâ 125-MHz 18-mm Quantum38K30 Quantum38K50 Quantum38K

    Untitled

    Abstract: No abstract text available
    Text: Quantum38K ISR™ CPLD Family PRELIMINARY CPLDs at ASIC Prices™ Features • High density — 30K to 100K usable gates — 512 to 1536 macrocells — 136 to 302 maximum I/O pins — 8 Dedicated Inputs including 4 clock pins and 4 global I/O control signal pins; 4 JTAG interface pins


    Original     		PDF Quantum38KTM 38K15 144FBGA MIL-STD-883" /JESD22-A114-A 83MHz 66MHz" 125MHz 83MHz" Quantum38K

    208EQFP

    Abstract: No abstract text available
    Text: Quantum38K ISR™ CPLD Family CPLDs Designed for Migration Features • High density — 30K to 100K usable gates — 512 to 1536 macrocells — 136 to 302 maximum I/O pins — Eight dedicated inputs including four clock pins and four global I/O control signal pins; four JTAG


    Original     		PDF Quantum38KTM 125-MHz 18-mm Quantum38K30 Quantum38K50 Quantum38K 208EQFP

    CY3LV010

    Abstract: 38K30 CYDH2200E 38K50
    Text: Quantum38K ISR™ CPLD Family PRELIMINARY CPLDs at ASIC Prices™ Features • High density — 30K to 100K usable gates — 512 to 1536 macrocells — 136 to 302 maximum I/O pins — Eight Dedicated Inputs including four clock pins and four global I/O control signal pins; four JTAG interface pins for reconfigurability/boundary scan


    Original     		PDF Quantum38KTM Quantum38K CY38K100 208-pin 208EQFP) CY3LV010 38K30 CYDH2200E 38K50

    WIDE BUS FAMILY

    Abstract: No abstract text available
    Text: Quantum38K ISR™ CPLD Family PRELIMINARY CPLDs at ASIC Prices™ Features • High density — 15K to 100K usable gates — 256 to 1536 macrocells — 92 to 302 maximum I/O pins — 8 Dedicated Inputs including 4 clock pins and 4 global control signal pins; 4 JTAG interface pins for


    Original     		PDF Quantum38KTM WIDE BUS FAMILY

    38K30

    Abstract: DELTA39K CY3LV010
    Text: USE DELTA39K FOR Quantum38K™ ISR™ ALL NEW DESIGNS CPLD Family CPLDs Designed for Migration Features • High density — 30K to 100K usable gates — 512 to 1536 macrocells — 136 to 302 maximum I/O pins — Eight dedicated inputs including four clock pins and


    Original     		PDF DELTA39KTM Quantum38KTM 16-Kb 48-Kb 125-MHz 18-mm Quantum38K30 Quantum38K50 Quantum38K Delta39K 38K30 CY3LV010