DSA0033548.pdf by Spectra Linear
- CY2SSTU877 1.8V, 500 MHz, 10-Output JEDEC-Compliant Zero Delay Buffer Features distributes a differential clock input pair (CK, CK#) to ten differential pair of clock outputs (Y[0:9], Y#[0:9]) an
- Original
- Unknown
- Unknown
- Unknown
-
Powered by
Findchips
